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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS, ICD | 2024-02-29 10:35 |
Okinawa | (Primary: On-site, Secondary: Online) |
Distributed Task Migration Algorithm for 3D Stacked Chips and Evaluation with actual measurement Takahiro Kanamori, Songxiang Wang, Kimiyoshi Usami (SIT)  VLD2023-109 HWS2023-69 ICD2023-98 |
The wireless communication technique between chips in a 3D stacked chip has a problem that certain areas are difficult t... [more] | VLD2023-109 HWS2023-69 ICD2023-98 pp.60-65 |
| CAS, SIP, VLD, MSS | 2022-06-16 16:10 |
Aomori | Hachinohe Institute of Technology (Primary: On-site, Secondary: Online) |
Dynamic Temperature Control Algorithm for 3-D Stacked Chips based on Thermal Analysis Songxiang Wang, Kimiyoshi Usami (Shibaura IT) CAS2022-10 VLD2022-10 SIP2022-41 MSS2022-10 |
The problem of heat generation is more serious in 3D stacked chips than in non-stacked counterparts. In this study, we f... [more] | CAS2022-10 VLD2022-10 SIP2022-41 MSS2022-10 pp.52-57 |
| CPM | 2021-10-27 10:30 |
Online | Online | Study on the low-temperature deposition method of SiNx film for Cu-TSV Masaru Sato, Mayumi B. Takeyama (Kitami Inst. of Tech.) CPM2021-21 |
For Cu through silicon via in the 3D-LSI, It is desired to realize a deposition method of an insulating film less than 2... [more] | CPM2021-21 pp.5-7 |
| CPM | 2020-10-29 14:00 |
Online | Online | Mechanism of Cu(111) orientation control on extremely thin barrier Mayumi B. Takeyama (Kitami Inst.& Technol.), Mitsunobu Yasuda (Toray Research Center.), Masaru Sato (Kitami Inst.& Technol.) CPM2020-14 |
In Si-LSI and/or 3D-LSI technology, it is strongly desired to obtain Cu(111) orientation with excellent electromigration... [more] | CPM2020-14 pp.11-14 |
| SDM | 2019-02-07 11:25 |
Tokyo | [Invited Talk]
Ultrafine 3D Interconnect Technology Using Directed Self-Assembly Takafumi Fukushima, Murugesan Mariappan, Mitsumasa Koyanagi (Tohoku Univ.) SDM2018-92 |
A directed self-assembly (DSA) technology is applied to fabricate ultrafine pitch TSV (Through-Silicon Vias) for ultra-h... [more] | SDM2018-92 pp.5-8 |
|
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-08 16:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | An Efficient Search Method on Stacked Rectangular Dissections Masaki Yokota, Kunihiro Fujiyoshi (TUAT) VLD2017-61 DC2017-67 |
For layout design of 3D-LSI, a stacked-rectangular-dissection, which consists of several rectangular dissections as... [more] |
VLD2017-61 DC2017-67 pp.247-252 |
| CPM | 2014-10-25 09:40 |
Nagano | Characterization of low-temperature deposited SiNx films applicable to 3D/2.5D-IC Mayumi B. Takeyama, Masaru Sato (Kitami Inst. of Tech.), Yasushi Kobayashi, Yoshihiro Nakata, Tomoji Nakamura (FUJITSU LAB.LTD.), Atsushi Noya (Kitami Inst. of Tech.) CPM2014-115 |
3-dimensional stacked LSI and/or 2.5-D IC is attracted much attention to solve the issues how to develop the integration... [more] | CPM2014-115 pp.53-56 |
|
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 10:00 |
Kanagawa | A Study of 3D FPGA Architecture Using Face-to-Face Stacked Routing Layer Yusuke Iwai, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2012-109 CPSY2012-58 RECONF2012-63 |
3D LSIs promise More than Moore integration by packing a great deal of functionality on a chip, while improving performa... [more] | VLD2012-109 CPSY2012-58 RECONF2012-63 pp.13-18 |
|
| ICD, SDM | 2012-08-02 14:40 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | Intra/Inter Tier Substrate Noise Measurements in 3D ICs Yasumasa Takagi, Yuuki Araga, Makoto Nagata (Kobe Univ.), Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Michael Libois, Antonio La Manna, Wenqi Zhang, Julien Ryckaert, Eric Beyne (IMEC) SDM2012-72 ICD2012-40 |
Substrate noise propagation among stacked dice is evaluated in a 3D test vehicle of 2 tier stacking. Each tier incorpora... [more] | SDM2012-72 ICD2012-40 pp.49-54 |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-26 13:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | An FPGA Implementation of Array Processor Performing 3D-DCT Effectively Yuki Ikegaki, Hiroyuki Igarashi, Toshiaki Miyazaki, Stanislav G. Sedukhin (Univ. of Aizu) VLD2009-76 CPSY2009-58 RECONF2009-61 |
Ordinary array processors randomly access to input-/coefficient-data in external memories many times during the 3D-DCT, ... [more] | VLD2009-76 CPSY2009-58 RECONF2009-61 pp.41-46 |
| SDM | 2008-03-14 15:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Compliant Micro-Bumps for 3D Stacked-Chip LSIs with High Density Interconnection Implemented at Low Temperature Naoya Watanabe (Kumamoto TIF), Yutaka Iwasaki, Tanemasa Asano (Kyushu Univ.) SDM2007-276 |
We have proposed the compliant bump. The compliant bump, which can be made in the shape of pyramid or cone, has the pote... [more] | SDM2007-276 pp.17-20 |
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