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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2010-04-23 13:45 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
Non-contact Chip-to-Chip Interfaces for 3D System Integration Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.)  ICD2010-16 |
Low cost, small size, low power, and wide-band non-contact area interfaces for inter-chip links in 3-D system integratio... [more] | ICD2010-16 pp.83-88 |
| ICD | 2010-04-23 15:15 |
Kanagawa | Shonan Institute of Tech. | An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR Inductive-Coupling Interface Between 65nm CMOS GPU and 0.1um DRAM Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda (Keio Univ.) ICD2010-18 |
An 8Tb/s 1pJ/b 0.8mm2/Tb/s inductive-coupling interface between 65nm CMOS GPU and 0.1um DRAM is developed. BER<10-16 ope... [more] | ICD2010-18 pp.93-97 |
| ICD | 2010-04-23 15:40 |
Kanagawa | Shonan Institute of Tech. | A 2Gb/s 1.8pJ/b/chip Inductive-Coupling Through-Chip Bus for 128-Die NAND-Flash Memory Stacking Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda (Keio Univ.) ICD2010-19 |
128 chips are stacked using a spiral stair stacking scheme. The controller accesses a random memory chip at 2Gb/s by ind... [more] | ICD2010-19 pp.99-102 |
| ICD | 2009-12-15 17:00 |
Shizuoka | Shizuoka University (Hamamatsu) | A 3D Processor Using Inductive-Coupling Inter-Chip Link
-- 3D System Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM -- Kiichi Niitsu (Keio Univ./JST), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga (Keio Univ.), Itaru Nonomura (Renesas Technology), Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie (Hitachi), Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Tadahiro Kuroda (Keio Univ.) ICD2009-105 |
A 90nm CMOS processor is mounted face down on a package by C4 bump and a 65nm CMOS 1MB SRAM is glued on it face up. The ... [more] | ICD2009-105 pp.163-168 |
| IN, NS, CS (Joint) |
2009-09-10 11:15 |
Miyagi | Tohoku University (Miyagi) | Design of Symbiotic 3D Virtual Space and Its Applications Hiroshi Noguchi, Hideyuki Takahashi, Takuo Suganuma, Norio Shiratori (Tohoku Univ.) IN2009-42 |
In our research, we are aiming to build infrastructure technology which to integrate/unite real space and virtual space... [more] |
IN2009-42 pp.17-22 |
| ED | 2009-07-31 11:15 |
Osaka | Osaka Univ. Icho-Kaikan | Study of Electroless Copper Plating for Through Si Via Filling Fumihiro Inoue, Takumi Yokoyama (Kansai Univ.), Kazuhiro Yamamoto, Shukichi Tanaka (NiCT), Shoso Shingubara (Kansai Univ.) ED2009-111 |
In recent studies, The formation of through-Silicon via hole (TSV) which stacks multiple layers of thin Si substrates is... [more] | ED2009-111 pp.47-50 |
| MI | 2009-01-20 11:30 |
Overseas | National Taiwan University | Visualization of 3D surface of human brain and multimodal information Jinyoung Hwang, Sung-Suk Oh, HyunWook Park (KAIST) MI2008-114 |
A 3D visual integration of diffusion tensor tractography and functional information from human brain MR images is an imp... [more] | MI2008-114 pp.255-256 |
| HIP | 2008-11-07 - 2008-11-11 |
Ishikawa | Kanazawa Institute of Technology, Yamahiro Hot Spring | [Invited Talk]
Integration of Multisensory Information and Human System Interactions Hiroshi Ando (National Institute of Information and Communications Technology) HIP2008-117 |
We developed a method for generating contact sounds smoothly and naturally according with a user's interactive hand acti... [more] | HIP2008-117 pp.159-161 |
| SDM | 2008-03-14 15:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Compliant Micro-Bumps for 3D Stacked-Chip LSIs with High Density Interconnection Implemented at Low Temperature Naoya Watanabe (Kumamoto TIF), Yutaka Iwasaki, Tanemasa Asano (Kyushu Univ.) SDM2007-276 |
We have proposed the compliant bump. The compliant bump, which can be made in the shape of pyramid or cone, has the pote... [more] | SDM2007-276 pp.17-20 |
| SDM | 2008-03-14 15:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Through-silicon Via Interconnection for 3D Integration Using Room-temperature Bonding Naotaka Tanaka, Yasuhiro Yoshimura, Michihiro Kawashita (Hitachi), Toshihide Uematsu, Takahiro Naitoh, Takashi Akazawa (Renesas) SDM2007-277 |
One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a 3D assembly are pot... [more] | SDM2007-277 pp.21-26 |
| NC, MBE (Joint) |
2008-03-12 15:20 |
Tokyo | Tamagawa Univ | Effect of spatial frequency variation on contour integration Masayuki Kikuchi, Hirotaka Tajima (Tokyo Univ. of Tech.) NC2007-123 |
A series of path-paradigm based experiments, which require subjects to detect a set of Gabor-patches placed along a smoo... [more] | NC2007-123 pp.67-71 |
| PRMU, HIP | 2007-02-23 16:00 |
Kanagawa | Face authentication system for large scale database by PCA of 3D face model fitted to range scan data Yusuke Nonaka, Nobuhiro Yamana, Akito Inbe, Fumihiro Miura, Akinobu Maejima, Shigeo Morishima (Waseda Univ.) |
In this paper, we propose an authentication system using 3D face geometry. We perform the principal component analysis f... [more] | PRMU2006-232 HIP2006-125 pp.61-66 |
|
| PRMU | 2006-03-17 13:30 |
Fukuoka | Kyushu Univ. | * , Takekazu Kato, Toshikazu Wada (Wakayama Univ.), (NICT) |
This paper presents a novel method for human head tracking using multiple cameras. Most existing methods estimate 3D tar... [more] | PRMU2005-277 pp.121-128 |
| ICD | 2005-05-26 11:30 |
Hyogo | Kobe Univ. | A Sheet-Type Scanner Based on a 3D Stacked Organic-Transistor Circuit with Double Word-line and Double Bit-line Structure Hiroshi Kawaguchi, Shingo Iba, Yusaku Kato, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai (Univ. of Tokyo) |
Double word-line and bit-line structure in an organic FET-based sheet-type scanner is described. This structure reduces ... [more] | ICD2005-23 pp.19-21 |
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