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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, IE, VLD, IPSJ-SLDM [detail] | 2015-10-26 15:25 |
Miyagi | A Power-Efficient Memory Hierarchy Design for the 3D Integration Era Wataru Uno, Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.)  VLD2015-30 ICD2015-43 IE2015-65 |
3D-stacked memories are expected to play key roles to realize high-performance and low-power computing systems. This pap... [more] | VLD2015-30 ICD2015-43 IE2015-65 pp.19-24 |
|
| RECONF | 2015-06-19 12:00 |
Kyoto | Kyoto University | An Area Optimization of 3D FPGA with high speed inter-layer communication link Yuto Takeuchi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2015-4 |
Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] | RECONF2015-4 pp.17-22 |
| SDM | 2015-01-27 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel A/D Converters Fabricated by Direct Bonding of SOI Layers Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake (NHK), Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto (The Univ. of Tokyo) SDM2014-141 |
We report the first demonstration of three-dimensional (3D) integrated CMOS image sensors with pixel-parallel A/D conver... [more] | SDM2014-141 pp.25-28 |
| HCGSYMPO (2nd) |
2014-12-17 - 2014-12-19 |
Yamaguchi | Kaikyo Messe Shimonoseki | An Application for Providing 3D Visual Experience of Up-to-date Food Stall Village in Kesennuma
-- integration with posts on social media -- Ryo Yamashita, Hiroki Uema (Kansai Univ.), Ryosuke Ichikari, Takeshi Kurata (AIST) |
The objective of our research is to develop a 3D application that can virtually experience up-to-date food stall village... [more] | |
| ICD, CPSY | 2014-12-02 11:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
The Evolution of CMOS Image Sensors Yusuke Oike (Sony) ICD2014-103 CPSY2014-115 |
This presentation introduces the evolution of CISs and their applications utilizing image quality, 3D integration, and w... [more] | ICD2014-103 CPSY2014-115 p.113 |
| CPM | 2014-10-25 09:40 |
Nagano | Characterization of low-temperature deposited SiNx films applicable to 3D/2.5D-IC Mayumi B. Takeyama, Masaru Sato (Kitami Inst. of Tech.), Yasushi Kobayashi, Yoshihiro Nakata, Tomoji Nakamura (FUJITSU LAB.LTD.), Atsushi Noya (Kitami Inst. of Tech.) CPM2014-115 |
3-dimensional stacked LSI and/or 2.5-D IC is attracted much attention to solve the issues how to develop the integration... [more] | CPM2014-115 pp.53-56 |
|
| RECONF | 2014-06-12 11:15 |
Miyagi | Katahira Sakura Hall | Three-dimensional FPGA Structure using High-speed Serial Communication Takuya Kajiwara, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-7 |
The three-dimensional (3D) integrated circuit technology is expected to continually improve the LSI (Large Scale Integra... [more] | RECONF2014-7 pp.31-36 |
| SDM | 2014-02-28 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Impact of Back Grind Damage on Si Wafer Thinning for 3D Integration Yoriko Mizushima (Fujitsu Lab./Tokyo Inst. of Tech.), Youngsuk Kim (Tokyo Inst. of Tech./Disco), Tomoji Nakamura (Fujitsu Lab.), Ryuichi Sugie, Hideki Hashimoto (Toray Research Center), Akira Uedono (Univ. of Tsukuba), Takayuki Ohba (Tokyo Inst. of Tech.) SDM2013-167 |
Ultra-thin wafer is indispensable for bumpless 3D stacking. To know the thinning damage in detail, an atomic level defec... [more] | SDM2013-167 pp.13-18 |
| SDM | 2014-02-28 13:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Keynote Address]
Integrated Circuits in Future
-- How do we find opportunity and challenge of integrated circuits? -- Kazuya Masu (Tokyo Inst. of Tech.) SDM2013-169 |
Based on the technology trend of integrated circuit, we discuss not only the future of integrated circuit, but the futur... [more] | SDM2013-169 pp.23-28 |
| SDM, ICD | 2013-08-01 11:10 |
Ishikawa | Kanazawa University | [Invited Talk]
3D-architecture technology movements and opportunity of Japan Hiroaki Ikeda (ASET) SDM2013-69 ICD2013-51 |
This is the overview of the world wide TSV/3D integration technology developments and State of the Art in Japan. Latter... [more] | SDM2013-69 ICD2013-51 pp.23-28 |
| CPM | 2013-08-02 10:55 |
Hokkaido | Barrier Properties of Nanocrystalline HfNx Films Applicable to Through Si Via Masaru Sato, Mayumi B. Takeyama (Kitami Inst. of Tech.), Eiji Aoyagi (Tohoku Univ.), Atsushi Noya (Kitami Inst. of Tech.) CPM2013-51 |
Through silicon via (TSV) technology is important to realize 3D integration by stacking chips or wafers. We propose conc... [more] | CPM2013-51 pp.63-68 |
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| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 10:00 |
Kanagawa | A Study of 3D FPGA Architecture Using Face-to-Face Stacked Routing Layer Yusuke Iwai, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2012-109 CPSY2012-58 RECONF2012-63 |
3D LSIs promise More than Moore integration by packing a great deal of functionality on a chip, while improving performa... [more] | VLD2012-109 CPSY2012-58 RECONF2012-63 pp.13-18 |
|
| HIP, ITE-HI, ITE-CE [detail] | 2011-11-11 12:45 |
Miyagi | RIEC | Integration of vision and proprioception on dynamic 3-D perception
-- Comparison between active and passive haptic perception -- Hiroyuki Umemura (AIST) HIP2011-52 |
In this study, I examined the integration of extra-retinal information and visual information. For the purpose, I conduc... [more] | HIP2011-52 pp.63-66 |
| ICD, ITE-IST | 2011-07-22 15:20 |
Hiroshima | Hiroshima Institute of Technology | [Invited Talk]
Implementation of Broadband Wireless Communication System Using Frequency-Domain Equalization Suguru Kameda (Tohoku Univ.) ICD2011-35 |
Frequency-domain equalization (FDE) method is necessary for realizing "Dependable Air", which is broadband and wide-ar... [more] |
ICD2011-35 pp.113-118 |
| ICD, IPSJ-ARC | 2011-01-20 14:20 |
Kanagawa | Keio University (Hiyoshi Campus) | [Invited Talk]
CMOS Hyper-Miniaturization and Cooperation with 3D System Design Integration Kazuya Okamoto, Ryohei Satoh (Osaka Univ.) |
Miniaturization technology based on Dennard’s rule for CMOS devices has been progressing technically over time and has c... [more] | ICD2010-131 p.29 |
| ICD, IPSJ-ARC | 2011-01-21 11:00 |
Kanagawa | Keio University (Hiyoshi Campus) | Performance Evaluation of 3D Integrated Multi-core Processors with Temperature Consideration Takaaki Hanada, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
In this paper, we evaluate three-dimensional (3D) multi-core processors with temperature constraint. 3D multi-core pro... [more] |
ICD2010-135 pp.51-56 |
| ICD | 2010-12-16 10:55 |
Tokyo | RCAST, Univ. of Tokyo | [Invited Talk]
Ambient Electronics and Integrated Circuits Takayasu Sakurai (Tokyo Univ.) ICD2010-97 |
Electronics is penetrating more into people's daily life and contributing more to society than ever. In this ubiquitous ... [more] | ICD2010-97 pp.13-18 |
| CAS (2nd) |
2010-10-06 11:45 |
Chiba | Makuhari Messe | [Invited Talk]
PI/SI/EMI simulation technology for high-speed electronic design Hideki Asai (Shizuoka Univ.) |
A variety of noise problems, such as signal integrity, power integrity and electromagnetic interference have become very... [more] | |
| ICD, SDM | 2010-08-27 10:15 |
Hokkaido | Sapporo Center for Gender Equality | [Invited Talk]
Development of sub-10um Thinning Technology using Actual Device Wafers Nobuhide Maeda, Kim Youngsuk (Univ. of Tokyo), Yukinobu Hikosaka, Takashi Eshita (FSL), Hideki Kitada, Koji Fujimoto (Univ. of Tokyo), Yoriko Mizushima (Fujitsu Labs.), Kousuke Suzuki (DNP), Tomoji Nakamura (Fujitsu Labs.), Akihito Kawai, Kazuhisa Arai (DISCO), Takayuki Ohba (Univ. of Tokyo) SDM2010-141 ICD2010-56 |
200-mm and 300-mm device wafers were successfully thinned down to less than 10-μm. A 200-nm non-crystalline layer remain... [more] | SDM2010-141 ICD2010-56 pp.95-97 |
| VLD, IPSJ-SLDM | 2010-05-20 10:00 |
Fukuoka | Kitakyushu International Conference Center | 3D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link Makoto Saen, Kenichi Osada, Yasuyuki Okuma (Hitachi), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Itaru Nonomura (Renesas Technology), Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Tadahiro Kuroda (Keio Univ.) VLD2010-5 |
This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chi... [more] | VLD2010-5 pp.43-47 |
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