| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2010-04-23 11:25 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
High-Speed Memory Interfaces
-- DDR/GDDR-DRAM -- Yasuhiro Takai (Elpida)  ICD2010-15 |
(To be available after the conference date) [more] | ICD2010-15 pp.81-82 |
| ICD | 2010-04-23 13:45 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
Non-contact Chip-to-Chip Interfaces for 3D System Integration Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.) ICD2010-16 |
Low cost, small size, low power, and wide-band non-contact area interfaces for inter-chip links in 3-D system integratio... [more] | ICD2010-16 pp.83-88 |
| ICD | 2010-04-23 15:40 |
Kanagawa | Shonan Institute of Tech. | A 2Gb/s 1.8pJ/b/chip Inductive-Coupling Through-Chip Bus for 128-Die NAND-Flash Memory Stacking Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda (Keio Univ.) ICD2010-19 |
128 chips are stacked using a spiral stair stacking scheme. The controller accesses a random memory chip at 2Gb/s by ind... [more] | ICD2010-19 pp.99-102 |
| ICD | 2009-12-15 17:00 |
Shizuoka | Shizuoka University (Hamamatsu) | A 3D Processor Using Inductive-Coupling Inter-Chip Link
-- 3D System Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM -- Kiichi Niitsu (Keio Univ./JST), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga (Keio Univ.), Itaru Nonomura (Renesas Technology), Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie (Hitachi), Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Tadahiro Kuroda (Keio Univ.) ICD2009-105 |
A 90nm CMOS processor is mounted face down on a package by C4 bump and a 65nm CMOS 1MB SRAM is glued on it face up. The ... [more] | ICD2009-105 pp.163-168 |
| SDM | 2008-03-14 15:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Compliant Micro-Bumps for 3D Stacked-Chip LSIs with High Density Interconnection Implemented at Low Temperature Naoya Watanabe (Kumamoto TIF), Yutaka Iwasaki, Tanemasa Asano (Kyushu Univ.) SDM2007-276 |
We have proposed the compliant bump. The compliant bump, which can be made in the shape of pyramid or cone, has the pote... [more] | SDM2007-276 pp.17-20 |
| SDM | 2008-03-14 15:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Through-silicon Via Interconnection for 3D Integration Using Room-temperature Bonding Naotaka Tanaka, Yasuhiro Yoshimura, Michihiro Kawashita (Hitachi), Toshihide Uematsu, Takahiro Naitoh, Takashi Akazawa (Renesas) SDM2007-277 |
One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a 3D assembly are pot... [more] | SDM2007-277 pp.21-26 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 11:05 |
Kanagawa | Hiyoshi Campus, Keio University | Implementation of 3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication Shotaro Saito, Yasufumi Sugimori, Yoshinori Kohama, Tadahiro Kuroda, Yohei Hasegawa, Hideharu Amano (Keio Univ.) VLD2007-123 CPSY2007-66 RECONF2007-69 |
This paper describes the physical design and evaluation of 3-D dynamically reconfigurable processor MuCCRA-Cube which co... [more] | VLD2007-123 CPSY2007-66 RECONF2007-69 pp.31-36 |
| RECONF | 2007-05-17 15:10 |
Ishikawa | Kanazawa Bunka Hall | 3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication MuCCRA-Cube Shotaro Saito, Yohei Hasegawa, Yoshinori Kohama, Yasufumi Sugimori, Hideharu Amano (Keio Univ.) RECONF2007-5 |
In typical dynamically reconfiguarable devices, the overhead for programmable wires often forms critical paths by stretc... [more] | RECONF2007-5 pp.25-30 |
[Return to Top Page]