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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS, ICD | 2024-02-29 10:35 |
Okinawa | (Primary: On-site, Secondary: Online) |
Distributed Task Migration Algorithm for 3D Stacked Chips and Evaluation with actual measurement Takahiro Kanamori, Songxiang Wang, Kimiyoshi Usami (SIT)  VLD2023-109 HWS2023-69 ICD2023-98 |
The wireless communication technique between chips in a 3D stacked chip has a problem that certain areas are difficult t... [more] | VLD2023-109 HWS2023-69 ICD2023-98 pp.60-65 |
| ICD, HWS | 2023-10-31 15:00 |
Mie | (Primary: On-site, Secondary: Online) |
Side-Channel Leakage Evaluation of 3D CMOS Chip Stacking Kazuki Monta, Rikuu Hasegawa, Takuji Miki, Makoto Nagata (Kobe Univ.) HWS2023-57 ICD2023-36 |
2.5D and 3D packaging are methodologies that include multiple integrated circuit (IC) chips. They deliver enhanced perfo... [more] | HWS2023-57 ICD2023-36 pp.16-19 |
| EE, OME, CPM | 2022-12-09 11:20 |
Tokyo | (Primary: On-site, Secondary: Online) |
Investigation for one-chip high functionality gate driver IC Yusuke Ogushi, Satoshi Matsumoto (KIT) EE2022-22 CPM2022-77 OME2022-35 |
GaN power devices have caught the attentions for high frequency switching and high efficiency of power supply. Our goal ... [more] | EE2022-22 CPM2022-77 OME2022-35 pp.18-23 |
| CAS, SIP, VLD, MSS | 2022-06-16 16:10 |
Aomori | Hachinohe Institute of Technology (Primary: On-site, Secondary: Online) |
Dynamic Temperature Control Algorithm for 3-D Stacked Chips based on Thermal Analysis Songxiang Wang, Kimiyoshi Usami (Shibaura IT) CAS2022-10 VLD2022-10 SIP2022-41 MSS2022-10 |
The problem of heat generation is more serious in 3D stacked chips than in non-stacked counterparts. In this study, we f... [more] | CAS2022-10 VLD2022-10 SIP2022-41 MSS2022-10 pp.52-57 |
| SDM | 2021-02-05 14:25 |
Online | Online | [Invited Talk]
Impacts of Misalignment on 1um Pitch Cu-Cu Hybrid Bonding Yoshihisa Kagawa, Takumi Kamibayashi, Masaki Haneda, Nobuotoshi Fujii, Syunsuke Furuse, Hideto Hashiguch, Tomoyuki Hirano, Hayato Iwamoto (SSS) SDM2020-58 |
In this study, we have successfully demonstrated the 1um pitch Cu-Cu hybrid bonding technology with remarkable electrica... [more] | SDM2020-58 pp.15-18 |
| MSS, CAS, SIP, VLD | 2020-06-18 14:25 |
Online | Online | Thermal transient analysis of the heat generation and design of temperature control circuit in three-dimensional stacked chip Tomoaki Oikawa, Kimiyoshi Usami (Shibaura Inst. of Tech.) CAS2020-9 VLD2020-9 SIP2020-25 MSS2020-9 |
As a technology for improving the degree of integration of LSI, there is a three-dimensional stacking technology of LSI ... [more] | CAS2020-9 VLD2020-9 SIP2020-25 MSS2020-9 pp.47-52 |
| SDM | 2020-02-07 14:55 |
Tokyo | Tokyo University-Hongo | [Invited Talk]
A THIN BONDING MATERIAL FOR HIGH DENSITY HETEROGENEOUS INTEGRATION Yasuhisa Kayaba, Yuzo Nakamura, Jun Kamada, Takashi Kozeki, Kazuo Kohmura (MCI) SDM2019-95 |
A new thin bonding material was developed for the heterogeneous device chip integration by Cu-Cu hybrid bonding. The bon... [more] | SDM2019-95 pp.31-34 |
| SDM | 2019-02-07 11:25 |
Tokyo | [Invited Talk]
Ultrafine 3D Interconnect Technology Using Directed Self-Assembly Takafumi Fukushima, Murugesan Mariappan, Mitsumasa Koyanagi (Tohoku Univ.) SDM2018-92 |
A directed self-assembly (DSA) technology is applied to fabricate ultrafine pitch TSV (Through-Silicon Vias) for ultra-h... [more] | SDM2018-92 pp.5-8 |
|
| VLD, CAS, MSS, SIP | 2016-06-17 15:10 |
Aomori | Hirosaki Shiritsu Kanko-kan | Clock Distribution Network with Multiple Source Buffers for Stacked Chips Nanako Niioka, Masashi Imai, Kaoru Furumi, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31 |
In this report, we present a method to reduce clock skew among stacked chips by a clock distribution network with multip... [more] | CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31 pp.167-172 |
| VLD, CAS, MSS, SIP | 2016-06-17 15:30 |
Aomori | Hirosaki Shiritsu Kanko-kan | Thermal Analysis in 3D ICs Kaoru Furumi, Masashi Imai, Nanako Niioka, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-32 VLD2016-38 SIP2016-66 MSS2016-32 |
Three-dimensional integrated circuits (3D ICs) lead to higher power densities than 2D ICs because of the stacking of mul... [more] | CAS2016-32 VLD2016-38 SIP2016-66 MSS2016-32 pp.173-178 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-20 09:00 |
Kanagawa | Hiyoshi Campus, Keio University | A Chip Evaluation of the Heat Generation in 3D stacked LSI Tatsuya Wada, Kimiyosi Usami (Shibaura IT) VLD2015-87 CPSY2015-119 RECONF2015-69 |
Heat is one of the problems in the three-dimensional stacking technology of LSI. We have developed a three-dimensional s... [more] | VLD2015-87 CPSY2015-119 RECONF2015-69 pp.85-90 |
| ICD, CPSY | 2014-12-02 11:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
The Evolution of CMOS Image Sensors Yusuke Oike (Sony) ICD2014-103 CPSY2014-115 |
This presentation introduces the evolution of CISs and their applications utilizing image quality, 3D integration, and w... [more] | ICD2014-103 CPSY2014-115 p.113 |
| CPM | 2014-10-25 09:40 |
Nagano | Characterization of low-temperature deposited SiNx films applicable to 3D/2.5D-IC Mayumi B. Takeyama, Masaru Sato (Kitami Inst. of Tech.), Yasushi Kobayashi, Yoshihiro Nakata, Tomoji Nakamura (FUJITSU LAB.LTD.), Atsushi Noya (Kitami Inst. of Tech.) CPM2014-115 |
3-dimensional stacked LSI and/or 2.5-D IC is attracted much attention to solve the issues how to develop the integration... [more] | CPM2014-115 pp.53-56 |
|
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2014-03-16 09:50 |
Okinawa | Voltage control considering the chip temperature in the three-dimensional stacked multi-core processors Yu Fujita, Yusuke Koizumi, Rie Uno, Hideharu Amano (Keio Univ.) CPSY2013-109 DC2013-96 |
Cube-1 is a prototype heterogeneous multiprocessor using inductive coupling wireless TCI (Through Chip Interface). Since... [more] | CPSY2013-109 DC2013-96 pp.241-246 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:00 |
Kagoshima | [Invited Talk]
Circuit design for 3D-stacking using TSV interconnects Kenichi Osada, Futoshi Furuta, Kenichi Takeda (Hitachi) VLD2013-73 CPM2013-117 ICD2013-94 CPSY2013-58 DC2013-39 RECONF2013-41 |
To improve the performance of 3D-stacking using TSV interconnects, circuit techniques were developed. To improve Z-axis ... [more] | VLD2013-73 CPM2013-117 ICD2013-94 CPSY2013-58 DC2013-39 RECONF2013-41 pp.93-96(VLD), pp.55-58(CPM), pp.55-58(ICD), pp.1-4(CPSY), pp.93-96(DC), pp.13-16(RECONF) |
|
| CPM | 2013-08-02 10:55 |
Hokkaido | Barrier Properties of Nanocrystalline HfNx Films Applicable to Through Si Via Masaru Sato, Mayumi B. Takeyama (Kitami Inst. of Tech.), Eiji Aoyagi (Tohoku Univ.), Atsushi Noya (Kitami Inst. of Tech.) CPM2013-51 |
Through silicon via (TSV) technology is important to realize 3D integration by stacking chips or wafers. We propose conc... [more] | CPM2013-51 pp.63-68 |
|
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 10:00 |
Kanagawa | A Study of 3D FPGA Architecture Using Face-to-Face Stacked Routing Layer Yusuke Iwai, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2012-109 CPSY2012-58 RECONF2012-63 |
3D LSIs promise More than Moore integration by packing a great deal of functionality on a chip, while improving performa... [more] | VLD2012-109 CPSY2012-58 RECONF2012-63 pp.13-18 |
|
| ICD, SDM | 2012-08-02 14:15 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | 3D Interconnect Technology by the Ultrawide-Interchip-Bus System for 3D Stacked LSI Systems Fumito Imura, Shunsuke Nemoto, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi, Hiroshi Nakagawa (AIST), Michiya Hagimoto, Hiroyuki Uchida, Takashi Omori, Yasumori Hibi, Yukoh Matsumoto (TOPS Systems), Masahiro Aoyagi (AIST) SDM2012-71 ICD2012-39 |
We have proposed the ultrawide-interchip-bus system for the interchip communication of the 3-dimentional stacked LSI sys... [more] | SDM2012-71 ICD2012-39 pp.43-48 |
| ICD, SDM | 2012-08-02 14:40 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | Intra/Inter Tier Substrate Noise Measurements in 3D ICs Yasumasa Takagi, Yuuki Araga, Makoto Nagata (Kobe Univ.), Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Michael Libois, Antonio La Manna, Wenqi Zhang, Julien Ryckaert, Eric Beyne (IMEC) SDM2012-72 ICD2012-40 |
Substrate noise propagation among stacked dice is evaluated in a 3D test vehicle of 2 tier stacking. Each tier incorpora... [more] | SDM2012-72 ICD2012-40 pp.49-54 |
| VLD, IPSJ-SLDM | 2010-05-20 10:00 |
Fukuoka | Kitakyushu International Conference Center | 3D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link Makoto Saen, Kenichi Osada, Yasuyuki Okuma (Hitachi), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Itaru Nonomura (Renesas Technology), Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Tadahiro Kuroda (Keio Univ.) VLD2010-5 |
This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chi... [more] | VLD2010-5 pp.43-47 |
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