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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2015-03-06
16:05
Kagoshima   A proposal of placement optimization algorithm by introducing TSV module
Atsushi Murata, Tomohiro Inaba, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC) CPSY2014-169 DC2014-95
The performance and the power efficiency of VLSI are expected to be significantly improved by the development of 3D stac... [more] CPSY2014-169 DC2014-95
pp.43-48
ICD, IE, SIP, IPSJ-SLDM [detail] 2011-10-24
14:20
Miyagi Ichinobo(Sendai) Three-Dimensional Accelerator Architecture for Image Recognition
Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) SIP2011-63 ICD2011-66 IE2011-62
Image recognition used widely in several areas needs high-performance and low power processor. Accelerator is an effecti... [more] SIP2011-63 ICD2011-66 IE2011-62
pp.7-12
ICD 2010-12-17
15:15
Tokyo RCAST, Univ. of Tokyo A Circuit Partitioning Strategy for 3-D Integrated Multipliers
Kazuhito Sakai, Jubee Tada (Yamagata Univ.), Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.), Gensuke Goto (Yamagata Univ.) ICD2010-125
Three-dimensional(3-D) integration technologies attract a lot of attention to further enhance the performance of the LSI... [more] ICD2010-125
pp.153-158
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