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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
14:10		 Kanagawa   Optimal Design and Performance Evaluation of Residue Arithmetic Circuits with a Binary Coding of Signed-Digit Number
Takuya Kobayashi, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2012-114 CPSY2012-63 RECONF2012-68		 Signed-Digit (SD) has a redundancy by using \{-1,0,1\}.
By applying the redundant binary representation to arithmetic c... [more]		 VLD2012-114 CPSY2012-63 RECONF2012-68
pp.39-44
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