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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| PRMU, BioX | 2019-03-18 14:15 |
Tokyo | Accelerating deep detectors based on tensor decomposition Hiroshi Hashimoto, Hitoshi Imaoka (NEC)  BioX2018-57 PRMU2018-161 |
(To be available after the conference date) [more] | BioX2018-57 PRMU2018-161 pp.163-168 |
|
| IBISML | 2019-03-06 13:30 |
Tokyo | RIKEN AIP | Acceleration of Boosting Discriminators Using Region Partition Learning and Its Application to Face Detectors Takeshi Mori, Junichi Takeuchi, Masanori Kawakita (Kyushu Univ.) IBISML2018-115 |
We propose a method of acceleration of boosting discriminators. Discriminant functions used for boosting are constructe... [more] |
IBISML2018-115 pp.73-80 |
| KBSE | 2019-03-02 11:30 |
Kyoto | Doshisha University Kambaikan | KBSE2018-66 |
(To be available after the conference date) [more] | KBSE2018-66 pp.75-80 |
| MSS, NLP (Joint) |
2018-03-13 15:45 |
Osaka | On Sector Decision Problem of Aircraft Positions in CARATS Open Data Shoya Tokumaru, Kunihiko Hiraishi (JAIST) MSS2017-86 |
Since February 2015 the Ministry of Land, Infrastructure and Transportation began offering data describing information o... [more] | MSS2017-86 pp.47-51 |
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| SIS | 2017-06-02 13:50 |
Oita | Housen-Sou (Beppu) | Study on Parameter Setting of the Dehazing Method with Adjustment of Transmittance Distribution Yi Ru, Go Tanaka (Nagoya City Univ.) SIS2017-20 |
In recent years, many dehazing methods have been investigated. We have proposed a dehazing method in which the degree of... [more] | SIS2017-20 pp.105-110 |
| PRMU, IE, MI, SIP | 2017-05-25 13:00 |
Aichi | Image Rearrangement for Vectorized Operations in FIR Filtering Yoshihiro Maeda, Shota Yamashita, Masahiro Nakamura, Norishige Fukushima, Hiroshi Matsuo (NIT) SIP2017-3 IE2017-3 PRMU2017-3 MI2017-3 |
In this paper, we focus vectorized programming for revisited FIR image filtering. We propose a new design pattern of ve... [more] |
SIP2017-3 IE2017-3 PRMU2017-3 MI2017-3 pp.13-18 |
|
| OCS, CS (Joint) |
2017-01-19 13:05 |
Fukuoka | Kyushu Sangyo University | Bipolar NRZ Coded Architecture for CAN FD and Its Performance Evaluation Takeyuki Shishido, Tatsuki Matsushita, Daisuke Umehara, Koichiro Wakasugi (Kyoto Inst. of Tech.) CS2016-64 |
Controller area network (CAN) is a communication standard that is widely employed for in-vehicle networks, and electroni... [more] | CS2016-64 pp.1-6 |
| COMP, ISEC | 2016-12-22 15:40 |
Hiroshima | Hiroshima University | Reduction of Search Number for Equivalence Structure Extraction Under Equivalence Structure Conservation Assumption Seiya Satoh (AIST), Yoshinobu Takahashi (University of Electro-Communications), Hiroshi Yamakawa (Dwango AI Lab) ISEC2016-87 COMP2016-48 |
We consider $K$-tuples that are composed of IDs that identify $K$D sequences where the number of IDs is $N$. An equivale... [more] | ISEC2016-87 COMP2016-48 pp.81-86 |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
High-Speed Operation of Program Voltage Generator for Low-voltage ReRAM Kenta Suzuki, Masahiro Tanaka, Kota Tsurumi, Ken Takeuchi (Chuo Univ.) ICD2016-67 CPSY2016-73 |
Resistive random access memory (ReRAM) is considered as one of the next generation non-volatile memories due to its high... [more] | ICD2016-67 CPSY2016-73 p.53 |
| PRMU | 2016-12-16 13:15 |
Tottori | PRMU2016-122 |
(To be available after the conference date) [more] | PRMU2016-122 pp.47-52 |
|
| MBE, NC (Joint) |
2016-11-18 15:55 |
Miyagi | Tohoku University | GPGPU-accelerated simulation and accuracy evaluation for various neuron models Shun Okuno (UEC), Kazuhisa Fujita (NIT), Yoshiki Kashimori (UEC) NC2016-32 |
To understand the processing mechanisms of sensory information in the brain, it is necessary to simulate a huge size of ... [more] | NC2016-32 pp.1-6 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2016-08-08 09:30 |
Nagano | Kissei-Bunka-Hall (Matsumoto) | Proposal of hash-based string matching algorithm for multiple-stream multiple-query using failure transition Kosuke Nishimura, Hiroaki Nishi (Keio Univ.) CPSY2016-10 |
Recently, the threat of attacks over the network is increasing. However, the security level depends on end-host users. T... [more] | CPSY2016-10 pp.1-6 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2016-08-09 10:30 |
Nagano | Kissei-Bunka-Hall (Matsumoto) | High Performance of Cache by Dynamic Control to Area Division Maika Tone, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo (Mie Univ.) CPSY2016-19 |
Today, multi-core processor is widely used to improve performance of a processor. However, memory access frequency of m... [more] |
CPSY2016-19 pp.119-124 |
| MBE, NC (Joint) |
2016-03-23 13:35 |
Tokyo | Tamagawa University | GPGPU-accelerated simulation of a sensory stimulus and neural activity Kazuhisa Fujita (INCT/ UEC), Yuki Abe, Koya Onodera, Yoshiki Kashimori (UEC) NC2015-84 |
It is important to know details of a sensory stimulus for understanding a nervous system. However, it is difficult to me... [more] | NC2015-84 pp.83-88 |
| NS, IN (Joint) |
2016-03-03 11:00 |
Miyazaki | Phoenix Seagaia Resort | A Study on Performance Improvement by Adaptive Selection of Data Optimaization in WAN Acceleration Technology Ryoichi Mutoh, Naoki Oguchi (Fujitsu Lab.) NS2015-189 |
WAN acceleration technology is a technique for improving the communication performance between a terminal and a server. ... [more] | NS2015-189 pp.123-128 |
| VLD | 2016-03-02 11:20 |
Okinawa | Okinawa Seinen Kaikan | Performance Improvement by Engineering Change Order in General-Synchronous Framework for Altera FPGA Hayato Mashiko, Takuya Oba, Yukihide Kohira (Univ. of Aizu) VLD2015-137 |
Recently, the logic circuits are implemented to FPGA instead of ASIC in many fields. However, the circuit implemented to... [more] | VLD2015-137 pp.149-154 |
| NS, RCS (Joint) |
2015-12-17 13:00 |
Ehime | Matsuyama Community Center | [Invited Lecture]
5G R&D Activities for High Data Rate and Low-Power-Consumption Radio Access Technologies with Higher-Frequency-Band and Wider-Bandwidth Massive MIMO Yukihiko Okumura, Satoshi Suyama (NTT DOCOMO), Toshifumi Sato, Yasushi Maruta (NEC), Akihiro Okazaki, Atsushi Okamura (Mitsubishi Electric), Akihiro Otaka, Jun Terada (NTT) NS2015-133 RCS2015-249 |
In this report, we introduce our 5G R&D activities for “High Data Rate and Low-Power-Consumption Radio Access Technologi... [more] | NS2015-133 RCS2015-249 pp.37-42(NS), pp.35-40(RCS) |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 16:20 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2015-51 DC2015-47 |
In layout design for LSI circuits, the layout area is minimized to reduce the fabrication cost and to increase the yield... [more] | VLD2015-51 DC2015-47 pp.81-86 |
| CS | 2015-07-02 10:10 |
Okinawa | Eef Information Plaza (Kumejima Is.) | Symbol Detection with OR Rule for CAN FD and Its Performance Evaluation Natsumi Sato, Daisuke Umehara, Koichiro Wakasugi (KIT) CS2015-11 |
Controller area network (CAN) is a communication standard for in-vehicle networks and is widely employed by a number of ... [more] | CS2015-11 pp.13-18 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-07 10:20 |
Kagoshima | Dynamic Scheduling Algorithm for Automatically Parallelized and Power Reduced Applications on Multicore Systems Takashi Goto, Kohei Muto, Tomohiro Hirano, Hiroki Mikami (Waseda Univ.), Uichiro Takahashi, Sakae Inoue (Fujitsu), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2014-178 DC2014-104 |
This paper proposes a dynamic scheduling algorithm for multiple automatically parallelized or power reduced applications... [more] | CPSY2014-178 DC2014-104 pp.95-100 |
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