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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] | 2019-07-24 13:45 |
Kochi | Kochi University of Technology | Design Space Search Applying Bayesian Optimization to High-level Design Flow Ryohei Nakayama (UTokyo), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo)  ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60 |
Now that circuit scale is increasing, high-level synthesis technology that designs circuits using high-level programming... [more] | ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60 pp.369-374 |
| RECONF | 2019-05-09 15:20 |
Tokyo | Tokyo Tech Front | High Level Synthesis of Recursive Description in a CPU+FPGA Co-design framework based on Ruby Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT) RECONF2019-6 |
(To be available after the conference date) [more] | RECONF2019-6 pp.29-34 |
| RECONF | 2019-05-09 15:45 |
Tokyo | Tokyo Tech Front | Hideki Takase (Kyoto Univ./JST), Kentaro Matsui (Kyoto Univ.), Yoshihiro Ueno (Delight Systems), Masakazu Mori (karabiner.inc), Susumu Yamazaki (Univ. of Kitakyushu) RECONF2019-7 |
(To be available after the conference date) [more] | RECONF2019-7 pp.35-40 |
| RECONF | 2019-05-10 11:15 |
Tokyo | Tokyo Tech Front | A case study of system development based on software hardware co-design using an FPGA/CPU mixed SoC
-- Implementation of the Julia set explorer using Ultra96 -- Kenta Sato, Yukinori Sato (TUT) RECONF2019-13 |
(To be available after the conference date) [more] | RECONF2019-13 pp.67-72 |
| HWS, VLD | 2019-02-27 12:40 |
Okinawa | Okinawa Ken Seinen Kaikan | Pattern Matching Based Detection of Wire Congestion from Source Code Description for High Level Synthesis Masato Tatsuoka, Mineo Kaneko (JAIST) VLD2018-96 HWS2018-59 |
When we use a high level synthesis (HLS) tool, the optimization of input code is necessary for obtaining an optimized ... [more] | VLD2018-96 HWS2018-59 pp.19-24 |
| HWS, VLD | 2019-02-27 14:30 |
Okinawa | Okinawa Ken Seinen Kaikan | Function-level Module Sharing with High-level Synthesis Ryohei Nozaki (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-100 HWS2018-63 |
High-Level Synthesis (HLS) which automatically synthesizes a Resister-Transfer Level (RTL) circuit from a behavioral des... [more] | VLD2018-100 HWS2018-63 pp.43-48 |
| HWS, VLD | 2019-03-01 10:00 |
Okinawa | Okinawa Ken Seinen Kaikan | Synthesis of Full Hardware Implementation of RTOS-Based Systems Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2018-122 HWS2018-85 |
This paper presents a method of automatically synthesizing a hardware design from a set of source codes for a real-time... [more] |
VLD2018-122 HWS2018-85 pp.175-180 |
| HWS, VLD | 2019-03-01 11:15 |
Okinawa | Okinawa Ken Seinen Kaikan | Synthesis of Distributed Control Circuits for Dynamic Scheduling across Multiple Dataflow Graphs Sayuri Ota, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2018-125 HWS2018-88 |
This article presents a method for synthesizing circuits with distributed control from CDFGs (control data flow graphs).... [more] | VLD2018-125 HWS2018-88 pp.193-198 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2019-01-31 13:35 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | VLD2018-87 CPSY2018-97 RECONF2018-61 |
(To be available after the conference date) [more] | VLD2018-87 CPSY2018-97 RECONF2018-61 pp.95-99 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 09:55 |
Hiroshima | Satellite Campus Hiroshima | Development of Software/Hardware Cooperative System for Radiosity Method using High-Level Synthesis with an FPGA Kotaro Tamura, Tetsu Narumi (UEC univ.) RECONF2018-34 |
The calculation cost of a Radiosity method is huge, since it takes into account the global illumination to produce reali... [more] | RECONF2018-34 pp.1-6 |
| RECONF | 2018-09-18 10:00 |
Fukuoka | LINE Fukuoka Cafe Space | RECONF2018-27 |
(To be available after the conference date) [more] | RECONF2018-27 pp.43-47 |
| RECONF | 2018-05-24 10:55 |
Tokyo | GATE CITY OHSAKI | Fumiya Kono, Naohito Nakasato (UoA) RECONF2018-2 |
(To be available after the conference date) [more] | RECONF2018-2 pp.7-12 |
| RECONF | 2018-05-24 11:20 |
Tokyo | GATE CITY OHSAKI | Prototyping of Dynamic Reconfiguration System to Execute Fallback Function Designed by High Level Synthesis Teruaki Sakata, Teppei Hirotsu (Hitachi) RECONF2018-3 |
We developed the architecture to execute a fallback operation when a failure occurred. In this research, we designed FPG... [more] | RECONF2018-3 pp.13-18 |
| VLD, HWS (Joint) |
2018-02-28 13:55 |
Okinawa | Okinawa Seinen Kaikan | Congestion Aware High Level Synthesis Design Flow with Source Compiler Masato Tatsuoka, Mineo Kaneko (JAIST) VLD2017-96 |
When we use a high level synthesis (HLS) tool, the optimization of input code is necessary for obtaining an optimized ... [more] | VLD2017-96 pp.43-48 |
| VLD, HWS (Joint) |
2018-02-28 14:20 |
Okinawa | Okinawa Seinen Kaikan | Development of Loop Flattening Tool that Reduces Cycle Overhead in Loop Pipelining of Nested Loops in High Level Synthesis Daisuke Ishikawa, Kenshu Seto (TCU) VLD2017-97 |
We develop a loop flattening tool for designing hardware with high level synthesis. When loop pipelining is applied to ... [more] | VLD2017-97 pp.49-54 |
| VLD, HWS (Joint) |
2018-02-28 16:55 |
Okinawa | Okinawa Seinen Kaikan | Reliability Evaluation of Mixed Error Correction Scheme for Soft-Error Tolerant Datapaths Junghoon Oh, Mineo Kaneko (JAIST) VLD2017-102 |
Among several problems with miniaturization of LSIs, soft-errors are one of serious problems to make reliability worse. ... [more] | VLD2017-102 pp.79-84 |
| VLD, HWS (Joint) |
2018-03-01 16:00 |
Okinawa | Okinawa Seinen Kaikan | A C Description Approach for High Level Synthesis to Configure DNN Inference Circuit Takuya Okamoto, Ryota Yamamoto, Shinya Honda (Nagoya Univ.) VLD2017-116 |
Today, Deep Neural Network (DNN) is utilized in various fields. There is a demand for deep learning in the field of embedd... [more] | VLD2017-116 pp.163-168 |
| VLD, HWS (Joint) |
2018-03-01 16:25 |
Okinawa | Okinawa Seinen Kaikan | A Concept of DNN Framework for Embedded System Using FPGA Ryota Yamamoto, Takuya Okamoto, Shinya Honda (Nagoya Univ.), Qian Zhao, Toki Matsumoto, Yukikazu Nakamoto (Hyogo Univ.), Tamotsu Sakai, Tetsuya Aoyama, Kazutoshi Wakabayashi (NEC) VLD2017-117 |
Recently, a DNN (Deep Neural Network) is used in many areas, and it required a field of an embedded system. For an em... [more] |
VLD2017-117 pp.169-174 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 15:35 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | VLD2017-72 CPSY2017-116 RECONF2017-60 |
(To be available after the conference date) [more] | VLD2017-72 CPSY2017-116 RECONF2017-60 pp.59-63 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 17:00 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Distributed Memory Architecture for High-Level Synthesis from Erlang Kagumi Azuma, Shoki Hamana, Hidekazu Wakabayashi, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) VLD2017-75 CPSY2017-119 RECONF2017-63 |
This paper presents a distributed memory architecture for dedicated hardware automatically synthesized from Erlang prog... [more] |
VLD2017-75 CPSY2017-119 RECONF2017-63 pp.77-82 |
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