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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS [detail] | 2022-03-07 10:00 |
Online | Online | A Heuristic Scheduling Algorithm with Variable-Cycle Approximate Operations in High-Level Synthesis Koyu Ohata, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritsumeikan Univ.)  VLD2021-78 HWS2021-55 |
This paper studies a scheduling algorithm for high-level synthesis that takes into account the difference in delay betwe... [more] | VLD2021-78 HWS2021-55 pp.13-18 |
| CAS, CS | 2022-03-04 13:45 |
Online | Online | Evaluation of Trojan Detector for AI Hardware Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) CAS2021-94 CS2021-96 |
In recent years, AI edge computing has been expanding to realize real-time inference by implementing AI models on edge d... [more] | CAS2021-94 CS2021-96 pp.106-111 |
| IE, ITS, ITE-AIT, ITE-ME, ITE-MMS [detail] | 2022-02-22 14:25 |
Online | Online | Development of a Real Camera System with High-Level Synthesis Hardware of Median-Based Dynamic Background Subtraction Kohei Shinyamada, Akira Yamawaki (Kyutech) ITS2021-61 IE2021-70 |
In this study, we developed a median-based dynamic background subtraction image processing system equipped with a real c... [more] | ITS2021-61 IE2021-70 pp.214-218 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 10:20 |
Online | Online | Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer Takuya Ando, Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2021-51 CPSY2021-20 RECONF2021-59 |
This article proposes a method for implementing a whole RTOS-based system as hardware using general-purpose high-level s... [more] | VLD2021-51 CPSY2021-20 RECONF2021-59 pp.13-18 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 10:45 |
Online | Online | Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems Yukino Shinohara, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2021-52 CPSY2021-21 RECONF2021-60 |
This paper presents hardware implementation of inter-task communication functions of RTOS, in the scheme where all the t... [more] | VLD2021-52 CPSY2021-21 RECONF2021-60 pp.19-24 |
| SANE | 2021-12-16 14:55 |
Chiba | Chiba University (Primary: On-site, Secondary: Online) |
Comparison of HLS and IP core for CP-SAR images processing onboard UAV Yuta Tanaka, Takumi Aoyama, Kazuteru Namba, Josaphat Tetuko Sri Sumantyo (Chiba Univ) SANE2021-76 |
(To be available after the conference date) [more] | SANE2021-76 pp.75-78 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-02 11:10 |
Online | Online | VLD2021-40 ICD2021-50 DC2021-46 RECONF2021-48 |
(To be available after the conference date) [more] | VLD2021-40 ICD2021-50 DC2021-46 RECONF2021-48 pp.133-138 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-02 11:35 |
Online | Online | Performance comparison of high-level synthesis tools using the gravitational many-body problem
-- On the difference between SDSoC and Vitis -- Akio Muramatsu, Tetsu Narumi (UEC) VLD2021-41 ICD2021-51 DC2021-47 RECONF2021-49 |
(To be available after the conference date) [more] | VLD2021-41 ICD2021-51 DC2021-47 RECONF2021-49 pp.139-143 |
| RECONF | 2021-09-10 09:55 |
Online | Online | An FPGA Implementation of neural networks with multi-core structured using high level synthesis Akira Jinguji, Hiroki Nakahara (Tokyo Tech) RECONF2021-18 |
(To be available after the conference date) [more] | RECONF2021-18 pp.7-12 |
| RECONF | 2021-09-10 15:45 |
Online | Online | RECONF2021-23 |
(To be available after the conference date) [more] | RECONF2021-23 pp.36-41 |
| HWS, VLD [detail] | 2021-03-03 14:55 |
Online | Online | Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2020-75 HWS2020-50 |
This article presents a revised architecture for full-hardware implementation of RTOS-based systems. In the previous m... [more] |
VLD2020-75 HWS2020-50 pp.38-43 |
| HWS, VLD [detail] | 2021-03-04 09:55 |
Online | Online | High-level synthesis of approximate circuits with two-level accuracies Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritumeikan Univ.) VLD2020-80 HWS2020-55 |
This paper studies high-level synthesis (HLS) of approximate computing circuits with multiple accuracy levels. This work... [more] | VLD2020-80 HWS2020-55 pp.67-72 |
| HWS, VLD [detail] | 2021-03-04 14:55 |
Online | Online | FPGA Implementation of Lightweight Cipher Chaskey through High-Level Synthesis and its Evaluation of Side-Channel Attack Resistance Saya Inagaki, Mingyu Yang (Tokyo Tech), Yang Li, Kazuo Sakiyama (UEC), Yuko Hara (Tokyo Tech) VLD2020-86 HWS2020-61 |
(To be available after the conference date) [more] | VLD2020-86 HWS2020-61 pp.102-107 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-26 13:10 |
Online | Online | Automated architecture exploration on Scala-based hardware development environment Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT) VLD2020-62 CPSY2020-45 RECONF2020-81 |
In recent years, reconfigurable architectures such as FPGAs have been attracting more and more attention. Design Space... [more] |
VLD2020-62 CPSY2020-45 RECONF2020-81 pp.131-136 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2020-02-27 17:00 |
Kagoshima | Yoron-cho Chuou-Kouminkan | HLS by multi-objective optimization under resource constraints
-- Approach to extracting coarse-grained parallelism using functional language -- Fukuhei Hamazaki, Tetsuro Yamazaki, Ryota Shioya (U-Tokyo), Kenichi Koizumi, Hiroshi Tezuka, Mary Inaba (U-Tokyo) CPSY2019-104 DC2019-110 |
For engineers who are not familiar with circuits, it is difficult to optimize circuit considering trade-off factors such... [more] | CPSY2019-104 DC2019-110 pp.99-104 |
| ICTSSL, CAS | 2020-01-30 18:00 |
Tokyo | High-level synthesis oriented histogram series duplication for overlapping continuous image processing Moena Yamasaki, Akira Yamawaki (Kyutech) CAS2019-80 ICTSSL2019-49 |
In order to quickly realize a high-performance and power-saving embedded image processing device, it is effective to use... [more] | CAS2019-80 ICTSSL2019-49 pp.85-89 |
|
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-23 11:50 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Binary Synthesis from RISC-V Executables Shoki Hamana, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2019-71 CPSY2019-69 RECONF2019-61 |
This article presents a method of synthesizing hardware from RISC-V binary codes. RISC-V is an open source instruction s... [more] | VLD2019-71 CPSY2019-69 RECONF2019-61 pp.111-115 |
| ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] | 2019-07-24 13:45 |
Kochi | Kochi University of Technology | Design Space Search Applying Bayesian Optimization to High-level Design Flow Ryohei Nakayama (UTokyo), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo) ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60 |
Now that circuit scale is increasing, high-level synthesis technology that designs circuits using high-level programming... [more] | ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60 pp.369-374 |
| RECONF | 2019-05-09 15:20 |
Tokyo | Tokyo Tech Front | High Level Synthesis of Recursive Description in a CPU+FPGA Co-design framework based on Ruby Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT) RECONF2019-6 |
(To be available after the conference date) [more] | RECONF2019-6 pp.29-34 |
| RECONF | 2019-05-09 15:45 |
Tokyo | Tokyo Tech Front | Hideki Takase (Kyoto Univ./JST), Kentaro Matsui (Kyoto Univ.), Yoshihiro Ueno (Delight Systems), Masakazu Mori (karabiner.inc), Susumu Yamazaki (Univ. of Kitakyushu) RECONF2019-7 |
(To be available after the conference date) [more] | RECONF2019-7 pp.35-40 |
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