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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS, ICD | 2024-03-01 14:00 |
Okinawa | (Primary: On-site, Secondary: Online) |
High-Level Synthesis Method for Python Considering Runtime Profiling Yusuke Suzuki, Makoto Ikeda (UTokyo)  VLD2023-127 HWS2023-87 ICD2023-116 |
With the increasing complexity of LSI design in recent years, high-level synthesis (HLS) technology has attracted attent... [more] | VLD2023-127 HWS2023-87 ICD2023-116 pp.145-150 |
| RECONF, VLD | 2024-01-29 11:20 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
VLD2023-82 RECONF2023-85 |
(To be available after the conference date) [more] | VLD2023-82 RECONF2023-85 pp.13-18 |
| RECONF, VLD | 2024-01-30 13:20 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems Kei Mikami, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2023-94 RECONF2023-97 |
This article presents a technique for handling increased number of tasks by reducing both circuit size and critical path... [more] | VLD2023-94 RECONF2023-97 pp.81-86 |
| RECONF, VLD | 2024-01-30 13:45 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Implementation of External Memory Access for Binary Synthesis Using General-Purpose High-Level Synthesizer Sho Kishimoto, Nagisa Ishiukra (Kwansei Gakuin Univ.) VLD2023-95 RECONF2023-98 |
In this article, we present a method for implementing external memory access within the context of binary synthesis util... [more] | VLD2023-95 RECONF2023-98 pp.87-92 |
| ICTSSL, CAS | 2024-01-25 11:00 |
Kanagawa | (Primary: On-site, Secondary: Online) |
Performance effect of memory access pattern for high-level synthesized sprite drawing hardware Yuka Otani, Akira Yamawaki (Kyutech) CAS2023-85 ICTSSL2023-38 |
We are developing a sprite drawing hardware suitable for high-level synthesis. Sprite drawing stores the sprite image in... [more] | CAS2023-85 ICTSSL2023-38 pp.17-22 |
| SIS | 2023-12-07 11:00 |
Aichi | Sakurayama Campus, Nagoya City University (Primary: On-site, Secondary: Online) |
Data Path Parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware Yuka Otani, Akira Yamawaki (Kyutech) SIS2023-24 |
A mobile terminal architecture which can dynamically reconfigure the optimal hardware for each application can achieve h... [more] | SIS2023-24 pp.1-6 |
| SIS | 2023-12-07 11:20 |
Aichi | Sakurayama Campus, Nagoya City University (Primary: On-site, Secondary: Online) |
Development of a real-time non-photorealistic rendering system with a high-level synthesized pencil drawing style image conversion hardware Honoka Tani, Akira Yamawaki (Kyutech) SIS2023-25 |
We developed non-photorealistic rendering (NPR) libraries optimized for high-level synthesis (HLS) technology that autom... [more] | SIS2023-25 pp.7-12 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 14:10 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Hardware obfuscation method using Obfuscator-LLVM and Bambu Mikiya Ogura, Shuichi Ichikawa (Toyohashi Univ. Tech.) VLD2023-54 ICD2023-62 DC2023-61 RECONF2023-57 |
Hardware obfuscation serves as a countermeasure against hardware reverse engineering. Yamada et al. employed the OLLVM s... [more] | VLD2023-54 ICD2023-62 DC2023-61 RECONF2023-57 pp.125-130 |
| MSS, CAS, SIP, VLD | 2023-07-06 09:30 |
Hokkaido | (Primary: On-site, Secondary: Online) |
Performance Improvement by Integrating Former and Latter Processes of Pencil Drawing Style Image Conversion on High-Level Synthesized Hardware. Honoka Tani, Akira Yamawaki (Kyutech) CAS2023-1 VLD2023-1 SIP2023-17 MSS2023-1 |
We are developing hardware to realize a high-performance and low-power embedded image processing device using high-level... [more] | CAS2023-1 VLD2023-1 SIP2023-17 MSS2023-1 pp.1-5 |
| MSS, CAS, SIP, VLD | 2023-07-06 10:10 |
Hokkaido | (Primary: On-site, Secondary: Online) |
Performance Improvement by Memory access and Process-level Pipelining for High-level Synthesized Sprite Drawing Hardware Yuka Otani, Akira Yamawaki (Kyutech) CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3 |
A mobile terminal with hardware reconfigurability can achieve higher performance and lower power consumption by performi... [more] | CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3 pp.10-15 |
| RECONF | 2023-06-08 16:00 |
Kochi | Eikokuji Campus, Kochi University of Technology (Primary: On-site, Secondary: Online) |
Parallelization of Prim's Algorithm Using FPGA and Its Performance Evaluation Noritsune O, Kenji Kanazawa, Moritoshi Yasunaga (Univ. of Tsukuba) RECONF2023-3 |
A subgraph of an undirected graph G that is connected and contains no closed paths is called a tree, a global tree is a ... [more] | RECONF2023-3 pp.13-16 |
| NLP, MSS | 2023-03-16 14:00 |
Nagasaki | (Primary: On-site, Secondary: Online) |
[Invited Talk]
Social Applications of FPGA and Machine Learning Yuichiro Shibata, Taito Manabe (Nagasaki Univ.) MSS2022-87 NLP2022-132 |
A field programmable gate array (FPGA) is a programmable device that allows users to configure logic circuits at their h... [more] | MSS2022-87 NLP2022-132 p.121 |
| RCC, ISEC, IT, WBS | 2023-03-14 14:15 |
Yamaguchi | (Primary: On-site, Secondary: Online) |
FPGA implementation of PQC Signature Algorithm QR-UOV using High Level Synthesis Kimihiro Yamakoshi, Tsunekaze Saito (NTT) IT2022-92 ISEC2022-71 WBS2022-89 RCC2022-89 |
QR-UOV has been proposed by Furue et al. as a signature scheme with security tolerance gainst quantum computers. QR-UOV... [more] | IT2022-92 ISEC2022-71 WBS2022-89 RCC2022-89 pp.149-154 |
| HWS, VLD | 2023-03-02 11:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
Automatic Synthesis of Decoupled Data Orchestration in High-Level Synthesis Masayuki Usui, Shinya Takamaeda (UTokyo) VLD2022-90 HWS2022-61 |
We automatically decouple data orchestration mechanisms in explicit data orchestration to facilitate accelerator design.... [more] | VLD2022-90 HWS2022-61 pp.103-108 |
| CAS, CS | 2023-03-01 14:50 |
Fukuoka | Kitakyushu International Conference Center (Primary: On-site, Secondary: Online) |
Memory access optimization for former process of pencil drawing style image conversion in High-level Synthesis Honoka Tani, Akira Yamawaki (Kyutech) CAS2022-105 CS2022-82 |
To effectively use high-level synthesis, which automatically converts software to hardware, it is necessary to create so... [more] | CAS2022-105 CS2022-82 pp.53-58 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-29 11:35 |
Kumamoto | (Primary: On-site, Secondary: Online) |
VLD2022-30 ICD2022-47 DC2022-46 RECONF2022-53 |
(To be available after the conference date) [more] | VLD2022-30 ICD2022-47 DC2022-46 RECONF2022-53 pp.67-71 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 17:05 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Implementation of stereo matching with Kria SOM toward precise field crop height measurement Ryo Nakagawa, Yoshiki Yamaguchi (Univ. of Tsukuba), Iman Firmansyah (BRIN) VLD2022-52 ICD2022-69 DC2022-68 RECONF2022-75 |
Xilinx's Kria K26 SOM is a credit card size module equipped with Zynq UltraScale+ equivalent SoC and DDR4 memory. Togeth... [more] | VLD2022-52 ICD2022-69 DC2022-68 RECONF2022-75 pp.188-193 |
| CAS, MSS, IPSJ-AL [detail] | 2022-11-18 16:00 |
Kochi | (Primary: On-site, Secondary: Online) |
An Investigation of Software Describing Methods to Design Parallax Background Scrolling Hardware in High-level Synthesis Kilryong Lee, Akira Yamawaki (KIT) CAS2022-59 MSS2022-42 |
We are developing a game programing library which can be converted to hardware modules by High-Level Synthesis, HLS tech... [more] | CAS2022-59 MSS2022-42 pp.105-110 |
| RECONF | 2022-06-07 13:50 |
Ibaraki | CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
Hardware implementation of the protocol for ROS2 and robot modules without CPU Daiki Matsunaga, Tomoya Shoji, Shozo Takeoka (AXE) RECONF2022-3 |
ROS2 is a set of software libraries and tools for robot applications. It is widely used in robot development. A ROS2 rob... [more] | RECONF2022-3 pp.13-19 |
| RECONF | 2022-06-08 09:45 |
Ibaraki | CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
Consideration of speeding up AI inference processing by cooperative operation of hardware and software Tomoya Kawakami, Chikako Nakanishi (OIT) RECONF2022-14 |
When cooperative processing of AI inference processing between software and hardware, it is difficult to analyze network... [more] | RECONF2022-14 pp.57-62 |
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