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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2014-02-10 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit Sanae Mizutani, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT)  DC2013-81 |
With the advances of semiconductor process technologies, synchronous circuits have serious problems of thr clock. Asynch... [more] | DC2013-81 pp.13-18 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 11:40 |
Kanagawa | Hiyoshi Campus, Keio University | Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption Tomoya Tasaki, Hiroto Kagotani, Yuji Sugiyama (Okayama Univ.) VLD2013-109 CPSY2013-80 RECONF2013-63 |
As one of the design methods of asynchronous pipeline circuits, a synthesis algorithm using dependency graphs has been p... [more] | VLD2013-109 CPSY2013-80 RECONF2013-63 pp.43-48 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-07 10:55 |
Aomori | Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) VLD2013-47 ICD2013-71 IE2013-47 |
There are mainly two types of handshaking protocols in asynchronous circuit design; 2-phase handshaking protocol and 4-p... [more] | VLD2013-47 ICD2013-71 IE2013-47 pp.7-12 |
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| IPSJ-SLDM, VLD | 2012-05-31 10:55 |
Fukuoka | Kitakyushu International Conference Center | Development of an FPGA Design Support Tool Set for Asynchronous Circuits with Bundled-data Implementation Keitaro Takizawa, Minoru Iizuka, Hiroshi Saito (Univ. of Aizu) VLD2012-9 |
This paper proposes a design support tool set for asynchronous circuits with bundled-data implemen-tation which are impl... [more] | VLD2012-9 pp.49-54 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:55 |
Miyazaki | NewWelCity Miyazaki | Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application Takao Kawano (Tohoku Univ.), Naoya Onizawa (McGill Univ.), Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.) VLD2011-89 DC2011-65 |
In this paper, a new fine-grained power-gating technique is proposed. Fine-grained power-gating technique has the potent... [more] | VLD2011-89 DC2011-65 pp.215-220 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 13:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | [Invited Talk]
Design of Asynchronous Circuits with Bundled-data Implementation on FPGA Hiroshi Saito (Univ. Aizu) VLD2010-107 CPSY2010-62 RECONF2010-76 |
This report initially introduces several researches related to asynchronous circuits and FPGAs. Then, this report propos... [more] | VLD2010-107 CPSY2010-62 RECONF2010-76 pp.157-162 |
| DC | 2010-06-25 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2010-8 |
Using asynchronous VLSI designs resolve synchronous circuit design difficulties, e.g.\ the clock skew, higher throughput... [more] | DC2010-8 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 10:40 |
Kochi | Kochi City Culture-Plaza | Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) CPM2009-135 ICD2009-64 |
Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] | CPM2009-135 ICD2009-64 pp.7-12 |
| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | A robust on-chip asynchronous data-transfer scheme based on multi-level current-mode signalling Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.), Tomohiro Yoneda (NII) DC2009-18 |
This paper presents a robust on-chip asynchronous data-trasnfer circuit based on multi-level current-mode signalling und... [more] | DC2009-18 pp.1-6 |
|
| VLD | 2009-03-12 17:30 |
Okinawa | Asynchronous $\pm2^k$ Gray-Code Adder Shinya Matsuyama, Takashi Hisakado (Kyoto Univ.) VLD2008-155 |
The topological property of Gray code, that only one bit of the code is changed when its representing integer is one inc... [more] | VLD2008-155 pp.171-176 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 14:45 |
Kanagawa | Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-120 CPSY2008-82 RECONF2008-84 |
Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] | VLD2008-120 CPSY2008-82 RECONF2008-84 pp.171-176 |
|
| ICD | 2008-12-12 14:35 |
Tokyo | Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan | Asynchronous ±1 Gray-Code Adder Shinya Matsuyama, Takashi Hisakado (Kyoto Univ.) ICD2008-124 |
The topological property of Gray Code, that only one bit of the code is changed when its representing integer is one inc... [more] | ICD2008-124 pp.113-118 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-19 11:15 |
Fukuoka | Kitakyushu Science and Research Park | Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors Koei Takada, Masashi Imai, Hiroshi Nakamura, Takashi Nanya (U. of Tokyo) VLD2008-90 DC2008-58 |
Dual-rail four-phase asynchronous circuits are well-known for their benefits in terms of delay variation tolerance. On t... [more] | VLD2008-90 DC2008-58 pp.183-188 |
| DC, CPSY | 2008-04-23 16:45 |
Tokyo | Tokyo Univ. | An approach to tolerating delay faults based on asynchronous circuits Tomohiro Yoneda (NII), Masashi Imai (Univ. of Tokyo), Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.), Yuichi Nakamura (NEC) CPSY2008-10 DC2008-10 |
Recent advances in semiconductor process technologies cause new types of faults, which should be handled in order to obt... [more] | CPSY2008-10 DC2008-10 pp.55-60 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-11-30 17:00 |
Fukuoka | Kitakyushu International Conference Center | Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) |
As the VLSI technology advances, delay variations will become more serious. Delay insensitive asynchronous dual-rail ci... [more] |
VLD2005-60 ICD2005-155 DC2005-37 pp.37-42 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-02 15:25 |
Fukuoka | Kitakyushu International Conference Center | Efficient contraction of timed signal transition graphs Tomohiro Yoneda (NII), Chris Myers (Univ. of Utah) |
In the decomposition based synthesis method, for each output signal, an input signal set sufficient to synthesize a cir... [more] |
VLD2005-86 ICD2005-181 DC2005-63 pp.59-64 |
| SCE | 2004-10-22 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Advanced Design Approaches for SFQ Logic Circuits based on the Binary Decision Diagram Takanobu Nishigai, Maki Ito, Nobuyuki Yoshikawa (Yokohama National Univ.), Koji Obata, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) |
We have been developing a design methodology of SFQ logic circuits based on the binary decision diagram(BDD). In the pre... [more] | SCE2004-27 pp.13-18 |
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