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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2021-02-05 10:30 |
Online | Online | A Study on a Method of Measuring Process Variations Considering the Effect of Wire Delay on FPGA Shingo Tsutsumi, Yukiya Miura (Tokyo Metropolitan Univ.)  DC2020-69 |
FPGAs are integrated circuits that can be implemented arbitrary logic functions. In FPGAs, it is important to measure pr... [more] | DC2020-69 pp.1-6 |
| VLD, IPSJ-SLDM | 2016-05-11 14:30 |
Fukuoka | Kitakyushu International Conference Center | A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-4 |
In deep-submicron era, interconnection delays are not negligible even in high-level synthesis. RDR (Regular Distributed ... [more] | VLD2016-4 pp.41-46 |
| VLD | 2016-03-01 15:10 |
Okinawa | Okinawa Seinen Kaikan | FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-127 |
Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS) are much focused on such as in image processing an... [more] | VLD2015-127 pp.93-98 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-54 DC2015-50 |
With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a cir... [more] | VLD2015-54 DC2015-50 pp.99-104 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 14:45 |
Oita | B-ConPlaza | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs Koichi Fujiwara, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-85 DC2014-39 |
Recently, high-level synthesis (HLS) techniques for FPGA designs are required such as in image pro- cessing and computer... [more] | VLD2014-85 DC2014-39 pp.99-104 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 15:10 |
Oita | B-ConPlaza | A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures Koki Igawa, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-86 DC2014-40 |
In this paper, we propose a process-variation-tolerant and low-latency multi-scenario high-level synthesis algorithm for... [more] | VLD2014-86 DC2014-40 pp.105-110 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:40 |
Oita | B-ConPlaza | A Distributed Router Architecture using transparent latches for Networks-on-Chip Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Tadao Nakamura (Keio Univ.) CPSY2014-80 |
Technology scaling creates NoC bottlenecks in both energy and delay, so especially wire delays and the power consumptio... [more] |
CPSY2014-80 pp.45-50 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:35 |
Oita | B-ConPlaza | Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-102 DC2014-56 |
An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis ... [more] | VLD2014-102 DC2014-56 pp.203-208 |
| SDM | 2014-02-28 10:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Trend of practical technology in advanced low-k integration Naoya Inoue (Renesas Electronics Corp.) SDM2013-166 |
Looking at the trend in Cu/Low-k interconnect technology, integration issues and solutions are discussed from the viewpo... [more] | SDM2013-166 pp.7-12 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 09:45 |
Kagoshima | An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-79 DC2013-45 |
With process technology scaling, decreasing reliability caused by soft errors as well as increasing the average intercon... [more] | VLD2013-79 DC2013-45 pp.129-134 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 11:40 |
Kagoshima | Clock Energy-efficient High-level Synthesis and Experimental Evaluation for HDR-mcd Architecture Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-97 DC2013-63 |
In this paper, we propose a clock energy-efficient high-level synthesis algorithm for HDR-mcd architecture. In HDR-mcd,... [more] |
VLD2013-97 DC2013-63 pp.263-268 |
|
| VLD, IPSJ-SLDM | 2013-05-16 16:00 |
Fukuoka | Kitakyushu International Conference Center | A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-9 |
In this paper, we propose a zero time and area overhead fault-secure high-level synthesis algorithm for RDR architecture... [more] | VLD2013-9 pp.67-72 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 11:20 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Temperature-Aware High-Level Synthesis Algorithm for Regular-Distributed-Register Architectures based on Accurate Energy Consumption Estimation Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-61 DC2012-27 |
With process technology scaling, heat problems in IC chips as well as increasing the average interconnection delays are ... [more] | VLD2012-61 DC2012-27 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 14:15 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | SAAV : Energy-efficient High-level Synthesis Algorithm targeting Adaptive Voltage Huddle-based Distributed Register Architecture with Dynamic Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology Univ./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-82 DC2012-48 |
An adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multip... [more] | VLD2012-82 DC2012-48 pp.135-140 |
| IPSJ-SLDM, VLD | 2012-05-30 14:55 |
Fukuoka | Kitakyushu International Conference Center | Multiple supply voltages aware high-speed and high-efficient high-level synthesis for HDR architectures Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-2 |
HDR architecture has been proposed as a platform that integrates energy-efficiency and interconnection delays into high-... [more] | VLD2012-2 pp.7-12 |
| VLD | 2011-03-04 15:55 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Evaluation of Wiring Resource and Wiring Delay used in Via Programmable Logic Device VPEX Tatsuya Kitamori, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2010-147 |
We have developed a via programmable logic device using exclusive-or array (VPEX). In a VPEX, the logic is changed using... [more] | VLD2010-147 pp.183-188 |
| VLD | 2010-03-11 10:50 |
Okinawa | Wiring delay of Logic Element used in Via programmable logic device VPEX Tomohiro Nishimoto, Tatsuya Kitamori, Yuuichi Kokushou, Shouta Yamada (Ritsumeikan Univ), Masaya Yoshikawa (Meijou Univ), Takeshi Fujino (Ritsumeikan Univ) VLD2009-109 |
We have been studied the via-programmable-device VPEX (Via Programmable logic using EXclusive or array) whose logic elem... [more] | VLD2009-109 pp.61-66 |
|
| VLD, IPSJ-SLDM | 2009-05-21 10:00 |
Fukuoka | Kitakyushu International Conference Center | A RST Construction Method for Vertices with Maximum Path Length Masafumi Inoue, Yoichi Tomioka (Tokyo Inst. of Tech.), Yukihide Kohira (the Univ. of Aizu), Atsushi Takahashi (Osaka Univ.) VLD2009-4 |
As the wire width decreases, the ratio of routing delay among signal propagation delay increases and the routing delay c... [more] | VLD2009-4 pp.31-36 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:55 |
Fukuoka | Kitakyushu Science and Research Park | Evaluation of Hardware Algorithms on a Circuit Model Considering Wire Delay Tetsuya Nagase, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) VLD2008-77 DC2008-45 |
In the design of integrated circuits, it is important to design or choose algorithms according to the requirements such ... [more] | VLD2008-77 DC2008-45 pp.103-108 |
| VLD, CAS, SIP | 2008-06-26 17:10 |
Hokkaido | Hokkaido Univ. | [Fellow Memorial Lecture]
A Consideration on Usage of CAD toolsfocused on
-- From Timing Analysis -- Shuji Tsukiyama (Chuo University) CAS2008-18 VLD2008-31 SIP2008-52 |
The design of integrated circuits consists of several phases, and for each phase, various Computer-Aided Design (CAD) to... [more] | CAS2008-18 VLD2008-31 SIP2008-52 pp.99-102 |
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