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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SCE | 2017-10-05 10:00 |
Miyagi | Applications of high-speed photon-number-resolving SNSPD array Hiroaki Myoren, Kazuki Ota, Satoshi Denda, Masato Naruse, Tohru Taino (Saitama Univ.), Lin Kang, Jian Chen, Peiheng Wu (Nanjing Univ.)  SCE2017-26 |
Photon-number resolving superconducting nanowire single photon detectors have been proposed using parallel and series co... [more] | SCE2017-26 pp.23-28 |
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| ET | 2017-03-10 12:45 |
Ehime | National Institute of Technology, Niihama College | Design of a training program for logic circuit and arithmetic algorithm learning using programmable devices Shigeki Abe (Tohoku Univ.) ET2016-112 |
(To be available after the conference date) [more] | ET2016-112 pp.105-110 |
| SP, SIP, EA | 2017-03-02 09:00 |
Okinawa | Okinawa Industry Support Center | [Poster Presentation]
NLMS algorithm using shift operation Takumi Miyake, Yoshinobu Kajikawa (Kansai Univ.) EA2016-129 SIP2016-184 SP2016-124 |
In the field of digital signal processing, an FPGA that can perform parallel processing and has a high calculation speed... [more] | EA2016-129 SIP2016-184 SP2016-124 pp.267-270 |
| ED | 2016-08-10 11:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | All-optical logic circuit using plasmonic multimode interference Masashi Ota, Asahi Sumimura, Ryo Watanabe, Kotaro Nakayama, Takahiro Furuki, Yuya Ishii, Mitsuo Fukuda (Toyohashi Univ. of Tech.) ED2016-41 |
Plasmonic logic circuits are of interest because of their potential for high-speed information processing and high-densi... [more] | ED2016-41 pp.61-64 |
| DC | 2016-06-20 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Random Test Pattern Generation based on Entropy Toshiaki Ohmameuda (Nat. Inst. Tech., Gunma Coll.) DC2016-13 |
In this paper the random test pattern generation method based on entropy is proposed. The circuits in this paper are c... [more] |
DC2016-13 pp.19-23 |
| VLD, CAS, MSS, SIP | 2016-06-16 10:10 |
Aomori | Hirosaki Shiritsu Kanko-kan | Automatic Test Pattern Generation for Multiple Stuck-At Faults: When Testing for Single Faults is Insufficient Conrad JinYong Moore, Amir Masoud Gharehbaghi, Masahiro Fujita (Univ. of Tokyo) CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3 |
As fabricated circuitry gets larger and denser, modern industrial ATPG techniques which focus on the detection of single... [more] | CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3 pp.13-18 |
| ET | 2015-03-14 10:35 |
Tokushima | Shikoku Univ. Plaza | Support tool for logic circuit lecture Hirokai Ishihata (Tokyo University of Technology) ET2014-97 |
We developed lecture materials for beginners' logic circuit course. Students are able to have deep understanding by exe... [more] |
ET2014-97 pp.65-69 |
| EMCJ, IEE-EMC | 2014-12-19 16:05 |
Shizuoka | Shizuoka Univ. | Security Evaluation of CSSAL Countermeasure against Side-Channel Attacks Using Frequency Spectrum Analysis Cancio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine (Gifu Univ.) EMCJ2014-82 |
Information leakage on cryptographic devices are possible because of the correlation between the processed data and its ... [more] | EMCJ2014-82 pp.75-80 |
| IT | 2014-07-17 10:35 |
Hyogo | Kobe University | On state change of FTM gate by using the orthogonal states Takaya Suzuki, Noboru Watanabe (TUS) IT2014-13 |
The FT gate is reversible and conservative logic gate proposed by Fredkin and Toffoli[2]. It's optical model is called a... [more] | IT2014-13 pp.13-16 |
| CAS | 2014-02-07 10:25 |
Kanagawa | Nippon Maru Training center | Comparison of energy consumption of the one or two phase adiabatic CMOS logic circuits Lin Zhao, Toshikazu Sekine, Yasuhiro Takahashi (Gifu Univ.) CAS2013-83 |
Adiabatic principle is one of the techniques for reducing power consumption of the circuit. In this paper, we are compa... [more] |
CAS2013-83 pp.53-57 |
| COMP | 2013-12-20 15:30 |
Okinawa | Okinawa Industry Support Center | [Tutorial Lecture]
Introduction to Computational Complexity Theory (5): Approaches to P vs. NP via Circuits Kazuhisa Seto (Seikei Univ.) COMP2013-47 |
In this talk, we give a brief introduction to Circuit Complexity and Circuit Satisfiability Problems. At first, we prov... [more] | COMP2013-47 p.57 |
| SCE | 2013-10-03 11:55 |
Miyagi | Tohoku University, RIEC | Design of SFQ digital circuit for photon number resolving detector using SNSPD Sunsuke Takeda, Masato Naruse, Tohru Taino, Hiroaki Myoren (Saitama Univ.), Jian Chen, Peiheng Wu (Nanjing Univ.) SCE2013-34 |
Superconducting nanowire single photon detectors (SNSPDs), those have a low dark count rate characteristics, fast and lo... [more] | SCE2013-34 pp.83-87 |
| IT | 2013-07-26 13:50 |
Tokyo | Nishi-Waseda campus, Waseda University | On construction of FTM gate by using the coherent control states Hideyuki Oki, Noboru Watanabe (TUS) IT2013-25 |
In this paper will discuss a mathematical construction of FTM gate by using coherent control status. [more] | IT2013-25 pp.69-73 |
| SCE | 2013-07-22 10:40 |
Tokyo | Kikaishinkou-kaikan Bldg. | Design and evaluation of the 2-bit Bit-Slice Adder based on 10kA/cm^2 process Kensuke Takata, Yuhi Hayakawa, Masamitsu Tanaka, Akira Fujimaki (Nagoya Univ.) SCE2013-12 |
A large number of researches on designing digital circuits by using SFQ logic circuits have been undertaken extensively.... [more] | SCE2013-12 pp.11-16 |
| OME, IEE-DEI | 2013-07-04 16:25 |
Niigata | [Invited Talk]
Fabrication of Stacked Logic Circuits for Printed Integrated Circuits Kazuhiro Kudo, Isao Kodera, Hiroshi Yamauchi, Shigekazu Kuniyoshi, Masatoshi Sakai (Chiba Univ.) OME2013-47 |
We have demonstrated logic circuit operations of stacked-structure thin film transistor (TFT) circuits using TIPS-pentac... [more] | OME2013-47 pp.25-30 |
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| IT | 2012-09-28 09:10 |
Gunma | Kusatsu Seminar House | Development of Generalized Encoder of BCH Code for Embedded System Nagamasa Mizushima, Yukihiro Takatani, Junji Ogawa, Atsushi Ishikawa (Hitachi) IT2012-36 |
For embedded systems that write data into flash memories at high speed, a parity of BCH code used for error correcting o... [more] | IT2012-36 pp.31-36 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 16:40 |
Kanagawa | Hiyoshi Campus, Keio University | Study of pattern area and reconfigurable logic circuit with DG/CNT transistor Takamichi Hayashi, Shigeyoshi Watanabe (SIT) VLD2011-119 CPSY2011-82 RECONF2011-78 |
Pattern area for 2~6 input reconfigurable logic circuit with double-gate (DG), Carbon-Nano-Tube (CNT), double-gate and C... [more] | VLD2011-119 CPSY2011-82 RECONF2011-78 pp.163-168 |
| SDM, ICD | 2011-08-25 09:50 |
Toyama | Toyama kenminkaikan | Study of pattern area for reconfigurable logic circuit with DG/CNT transistor Takamichi Hayashi, Shigeyoshi Watanabe (SIT) SDM2011-73 ICD2011-41 |
Pattern area for 2~6 input reconfigurable logic circuit with double-gate (DG), Carbon-Nano-Tube (CNT), double-gate and C... [more] | SDM2011-73 ICD2011-41 pp.13-16 |
| NC, NLP | 2011-01-24 10:20 |
Hokkaido | Hokakido Univ. | Dynamical Logic Circuit with Chaotic Transition Using Switched-Capacitor Chaotic Neuron Circuits Kazuyoshi Ishimura (TDU), Jun Takahashi (AIHARA Co., Ltd.), Yoshihiko Horio (TDU), Kazuyuki Aihara (Tokyo Univ.) NLP2010-127 NC2010-91 |
Complex responses including chaotic responses were observed through physiological experiments with biological neurons. T... [more] | NLP2010-127 NC2010-91 pp.13-18 |
| SDM | 2010-11-12 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Modeling of Single-Event-Transient Pulse Generation in Inverter Cells Katsuhiko Tanaka, Hideyuki Nakamura, Taiki Uemura, Kan Takeuchi, Toshikazu Fukuda, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete) SDM2010-180 |
Soft errors in logic circuits due to the propagation of erroneous signal caused by ionized particle generated by cosmic ... [more] | SDM2010-180 pp.47-52 |
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