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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] |
2022-01-25 13:15 |
Online |
Online |
A Study on Technology mapping method for Scalable Logic Module Izumi Kiuchi, Yuya Nakazato (Kumamoto Univ.), Qian Zhao (KIT), Masahiro Iida (Kumamoto Univ.) VLD2021-68 CPSY2021-37 RECONF2021-76 |
The LUT (Lookup Table) , which is widely used as the logic cell in FPGA (Field Programmable Gate Array), can implement a... [more] |
VLD2021-68 CPSY2021-37 RECONF2021-76 pp.108-113 |
CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] |
2021-01-26 12:45 |
Online |
Online |
SLM based FPGA-IP soft core Yuya Nakazato, Hiroaki Koga (Kumamoto Univ.), Zhao Qian (KIT), Motoki Amagasaki, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) VLD2020-61 CPSY2020-44 RECONF2020-80 |
In the recent edge computing infrastructure, MEC (Multi-access Edge Computing) devices is considered to reduce the load ... [more] |
VLD2020-61 CPSY2020-44 RECONF2020-80 pp.125-130 |
RECONF |
2015-06-20 16:15 |
Kyoto |
Kyoto University |
A Technology Mapping Method for Scalable Logic Module Ryo Araki, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2015-27 |
In order to implement logic functions, conventional field-programmable gate arrays (FPGAs) employs look-up tables (LUTs)... [more] |
RECONF2015-27 pp.147-152 |
RECONF |
2013-09-19 09:25 |
Ishikawa |
Japan Advanced Institute of Science and Technology |
A LUT Architecture Based on Partial Function of Shannon Expansion Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-27 |
In order to implement logic functions, conventional eld programmable gate arrays (FPGAs) employs look-up tables (LUTs) ... [more] |
RECONF2013-27 pp.43-48 |
RECONF |
2010-09-17 09:25 |
Shizuoka |
Shizuoka University (Faculty of Eng., Hall 2) |
COGRE: A Novel Compact Logic Cell Architecture for Area Reduction Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-31 |
In order to implement logic functions, conventional field programmable gate arrays (FPGAs) adopt look-up tables (LUTs) a... [more] |
RECONF2010-31 pp.79-84 |
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