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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2020-11-18
09:55
Online Online Seat Layout Method Considering Physical Distance Using Cell Placement Methods in LSI
Yukihide Kohira (Univ. of Aizu) VLD2020-34 ICD2020-54 DC2020-54 RECONF2020-53
Due to the spread of COVID-19 infection, it is required to secure a physical distance between people. In this paper, the... [more] VLD2020-34 ICD2020-54 DC2020-54 RECONF2020-53
pp.127-131
CAS, SIP, MSS, VLD 2018-06-14
16:15
Hokkaido Hokkaido Univ. (Frontier Research in Applied Sciences Build.) Acceleration of Analytical Placement by Wire Length Prediction using Machine Learning
Tatsuki Hoshiba, Yukihide Kohira (Univ. of Aizu) CAS2018-14 VLD2018-17 SIP2018-34 MSS2018-14
In recent LSI design, it is difficult to obtain a placement that satisfies both design constraints and specifications du... [more] CAS2018-14 VLD2018-17 SIP2018-34 MSS2018-14
pp.75-80
VLD, IPSJ-SLDM 2015-05-14
09:40
Fukuoka Kitakyushu International Conference Center Use of the subgradient method to minimize half perimeter wirelength with consideration of cell overlap in analytical placement
Hiroyuki Iwasaki, Hiroshi Miyashita (The Univ. of Kitakyushu) VLD2015-2
Placement continues to be one of the most important tasks in electronic design automation (EDA)
to handle the continua... [more]
VLD2015-2
pp.7-12
VLD, IPSJ-SLDM 2014-05-29
09:20
Fukuoka Kitakyushu International Conference Center A Subgradient Method for Analytical Minimization of Half-Perimeter Wirelength
Sohta Kayama, Hiroshi Miyashita (Univ. of Kitakyushu) VLD2014-3
In this paper, we propose a subgradient method to minimize half-perimeter wire length(HPWL) for circuit placement. Among... [more] VLD2014-3
pp.13-18
VLD 2013-03-04
15:45
Okinawa Okinawa Seinen Kaikan TSV-aware Analytical Placement
Koji Morita, Yasuhiro Takashima (Univ. of Kitakyushu) VLD2012-140
In this paper, we propose a TSV-aware anlytical placement. Recently, to implement much large-scale LSI, a multi-layer LS... [more] VLD2012-140
pp.25-29
VLD 2013-03-04
16:35
Okinawa Okinawa Seinen Kaikan The minimum perturbation placement realization for convex blocks
Hiroki Matsugano, Shota Hirae, Yasuhiro Takashima (Univ. of Kitakyushu) VLD2012-142
In this paper, we propose the minimum perturbation placement realizetion for the convex blocks. The method is enhanced m... [more] VLD2012-142
pp.37-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
09:25
Fukuoka Centennial Hall Kyushu University School of Medicine An Acceleration Method by GPGPU for Analytical Placement using Quasi-Newton Method
Yukihide Kohira (UoA), Yasuhiro Takashima (Univ. of Kitakyushu) VLD2012-74 DC2012-40
In this paper, we propose an acceleration method by GPGPU for an analytical placement method using a quasi-Newton method... [more] VLD2012-74 DC2012-40
pp.87-92
IPSJ-SLDM, VLD 2011-05-18
14:40
Fukuoka Kitakyushu International Conference Center An Effective Overlap Removable Objective for Analytical Placement
Syota Kuwabara, Yukihide Kohira (Univ. of Aizu), Yasuhiro Takashima (Univ. of Kitakyushu) VLD2011-2
In the recent LSI design, it is difficult to obtain the placement which satisfies design constraints and specifications ... [more] VLD2011-2
pp.7-12
SIP, CAS, VLD 2009-07-02
13:10
Hokkaido Kushiko-shi Shogai Gakushu Center 3D Placement Based on Stable-LSE
Masatomo Kuwano, Naoto Funatsu, Yasuhiro Takashima (Univ. of Kitakyushu) CAS2009-17 VLD2009-22 SIP2009-34
We propose a 3D analytical placement based on Stable-LSE in order to minimize the total wire-length and the overlap volu... [more] CAS2009-17 VLD2009-22 SIP2009-34
pp.91-96
 Results 1 - 9 of 9  /   
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