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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2023-06-09 15:20 |
Kochi | Eikokuji Campus, Kochi University of Technology (Primary: On-site, Secondary: Online) |
 RECONF2023-13 |
(To be available after the conference date) [more] | RECONF2023-13 pp.68-73 |
| HWS, VLD | 2019-02-27 13:05 |
Okinawa | Okinawa Ken Seinen Kaikan | Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-97 HWS2018-60 |
In this report, we consider a wire load model for an FPGA using new nano-device called via-switch to allow power estimat... [more] | VLD2018-97 HWS2018-60 pp.25-30 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-24 09:00 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan | Deduplication Estimation System for Large Scale Enterprise Storage Kazuei Hironaka, Tomohiro Kawaguchi (Hitachi) CPSY2017-10 DC2017-10 |
In recent years, the amount of data handled by enterprise information systems is explodingly increasing. In order to ... [more] |
CPSY2017-10 DC2017-10 pp.51-54 |
| CQ, ICM, NS (Joint) |
2015-11-27 09:25 |
Niigata | Niigata University | [Encouragement Talk]
Assessment for Runbook Automation Based on Indexes of Concreteness of Operational Manuals Takashi Yanase, Isao Namba (Fujitsu Labs Ltd.) ICM2015-23 |
An accurate prior estimation of development volume is necessary for an assessment based on cost-effectiveness when the i... [more] | ICM2015-23 pp.33-38 |
| KBSE | 2012-03-16 11:40 |
Aichi | Nagoya Univ. | Case study for identifying estimation risk in contract-base software projects Masato Notomi, Takako Nakatani (Univ. of Tsukuba) |
In a contract-base software project, the developer might prepare the estimation, before identifying all the requirements... [more] | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-28 10:55 |
Miyazaki | NewWelCity Miyazaki | High accuracy of system LSI energy estimation Wang Xiang (Kyushu Univ.), Norifumi Yoshimatsu (ISIT), Kazuaki Murakami (Kyushu Univ.) VLD2011-56 DC2011-32 |
The goal of this paper is that how to estimate the energy consumption of LSI system accurately with the high simulation ... [more] | VLD2011-56 DC2011-32 pp.25-30 |
| KBSE | 2011-11-10 13:20 |
Nagano | Shinshu Univ. | Towards a method for reducing estimation risk in contract-base software projects Masato Notomi, Takako Nakatani (Univ. of Tsukuba) KBSE2011-40 |
In a contract-base software project, the developer might prepare the estimation, before identifying all the requirements... [more] | KBSE2011-40 pp.25-30 |
| VLD | 2010-09-28 15:50 |
Kyoto | Kyoto Institute of Technology | Modeling of Latching Probability of Soft-Error-Induced Pulse Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga (Kyusyu Univ.) VLD2010-56 |
This paper describes soft error which is one of the dependability decrease factors of LSI(Large Scale Integrated circuit... [more] | VLD2010-56 pp.83-88 |
| SS | 2010-08-05 11:30 |
Hokkaido | Asahikawa Shimin-Bunka-Kaikan (Civic Culture Hall) | Requirement Analysis for Low Energy Consumption with Keeping User Satisfaction
-- Rearrangement Specification with Development Cost -- Ryu Nakazato, Takanobu Ando, Tetsuji Fukaya (Toshiba Corp) SS2010-18 |
Low energy consumption is one big issue. We study about requirement analysis for low energy consumption with keeping use... [more] | SS2010-18 pp.11-16 |
| VLD | 2010-03-11 15:00 |
Okinawa | Fast Estimation Method of Peak Power considered Input Vector and Inner State of a Circuit Nobuyoshi Takahashi (Tokyo Inst. of Tech.), Yoichi Tomioka (Tokyo Univ. of Agriculture and Tech.), Yukihide Kohira (The Univ. of Aizu), Atsushi Takahashi (Osaka Univ.) VLD2009-115 |
The peak power of a clock synchronous circuit is requested to be small to reduce the influence on circuit performance an... [more] | VLD2009-115 pp.97-102 |
|
| VLD, CAS, SIP | 2008-06-26 17:10 |
Hokkaido | Hokkaido Univ. | [Fellow Memorial Lecture]
A Consideration on Usage of CAD toolsfocused on
-- From Timing Analysis -- Shuji Tsukiyama (Chuo University) CAS2008-18 VLD2008-31 SIP2008-52 |
The design of integrated circuits consists of several phases, and for each phase, various Computer-Aided Design (CAD) to... [more] | CAS2008-18 VLD2008-31 SIP2008-52 pp.99-102 |
| VLD, IPSJ-SLDM | 2008-05-09 11:40 |
Hyogo | Kobe Univ. | Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) VLD2008-9 |
This paper describes analysis of on-chip bus power in the presence of arrival time variations of input signals. With shr... [more] | VLD2008-9 pp.13-18 |
| VLD, ICD | 2008-03-06 15:05 |
Okinawa | TiRuRu | Performance Estimation considering False-paths for System-level Design Daisuke Ando, Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita (Univ. of Tokyo) VLD2007-152 ICD2007-175 |
In designing today's highly complicated system-LSIs, it is essential to estimate timing information such as worst-case o... [more] | VLD2007-152 ICD2007-175 pp.49-54 |
| CAS | 2008-02-01 09:50 |
Okinawa | A High Fidelity Estimation Method for Interconnect Delays with a Ramp Input Daisuke Orui, Shuji Tsukiyama (Chuo Univ.) CAS2007-96 |
With the progress of micro-technologies, the importance of interconnect design has been increasing. Since delays must b... [more] | CAS2007-96 pp.13-18 |
|
| NS, IN (Joint) |
2007-03-09 13:10 |
Okinawa | Okinawa Convention Center | Estimating Response Time and Availability of Composite Web Services from BPEL Workflow Hirotaka Maeshima, Yoji Onishi, Masahide Nakamura, Ken-ichi Matsumoto (NAIST) IN2006-258 |
The users of Web service have been given chances to select the high quality services from many services, because of the ... [more] | IN2006-258 pp.465-470 |
| SDM, VLD | 2006-09-25 13:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Peak Power Reduction in LSI by Clock Scheduling Yosuke Takahashi, Atsushi Takahashi (Tokyo Tech) |
The reduction of peak power consumption of LSI is required to reduce the instability of gate operation, the delay increa... [more] | VLD2006-35 SDM2006-156 pp.7-12 |
| SIP, CAS, VLD | 2006-06-22 13:30 |
Hokkaido | Kitami Institute of Technology | Area/delay Estimation for Application Processor Daisuke Yamazaki, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
This paper proposes an area/delay estimation method with configurable pipeline stages and controller structure.In HW/SW ... [more] | CAS2006-1 VLD2006-14 SIP2006-24 pp.1-6 |
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-21 14:00 |
Miyagi | Ichinobo, Sakunami-Spa | A Reliability Evaluation Technique for Soft-Error Susceptible Computer Systems Makoto Sugihara (ISIT), Tohru Ishihara (Kyushu Univ.), Koji Hashimoto (Fukuoka Univ.), Masanori Muroyama (Kyushu Univ.) |
As the feature size of integrated circuits shrinks, their voltage and noise margins are lowered and the soft error issue... [more] | SIP2005-123 ICD2005-142 IE2005-87 pp.49-54 |
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