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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]		 2021-12-02
11:10		 Online Online VLD2021-40 ICD2021-50 DC2021-46 RECONF2021-48 (To be available after the conference date) [more] VLD2021-40 ICD2021-50 DC2021-46 RECONF2021-48
pp.133-138
DC, SS 2019-10-24
16:00		 Kumamoto Kumamoto Univ. A Non-scan Online Test Based on Covering n-Time State Transition
Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) SS2019-19 DC2019-47		 As one of the means to avoid the fault due to the deteriorate over time of VLSI, online test is used to monitor the outp... [more] SS2019-19 DC2019-47
pp.37-42
DC 2014-02-10
12:25		 Tokyo Kikai-Shinko-Kaikan Bldg. An Efficient Test Pattern Generator based on Mersenne Twister algorithm
Sayaka Satonaka, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-86		 To perform a high reliable manufacturing test with a reasonable cost, LFSR is widely used as test pattern generator. How... [more] DC2013-86
pp.43-48
DE, DC 2007-10-16
11:30		 Tokyo Kikai-Shinko-Kaikan Bldg Evaluation Model of Pseudo Random Pattern Quality for Logic BIST
Satoshi Fukumoto, Harunobu Kurokawa, Masayuki Arai, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.) DE2007-124 DC2007-21		 In this paper, we discuss the stochastic and statistical analyses on the distribution of fault coverage in random-patter... [more] DE2007-124 DC2007-21
pp.51-56
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