IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 35  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2023-11-17
14:10
Kumamoto Civic Auditorium Sears Home Yume Hall
(Primary: On-site, Secondary: Online)
Configuration Data Compression for SLM Fine-grained Reconfigurable Logic
Souhei Takagi, Takuya Kozima, Hideharu Amano (Keio Univ), Morihiro Kuga, Masahiro Iida (Kumamoto Univ) VLD2023-72 ICD2023-80 DC2023-79 RECONF2023-75
SLM (Scalable Logic Module) is a fine-grained reconfigurable logic developed by Kumamoto University, characterized by it... [more] VLD2023-72 ICD2023-80 DC2023-79 RECONF2023-75
pp.215-220
CPSY, DC, IPSJ-ARC [detail] 2023-08-04
18:20
Hokkaido Hakodate Arena
(Primary: On-site, Secondary: Online)
Power Evaluation of "SLMLET" Chip with Mixed RISC-V MP and SLM Reconfiguration Logic
Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ./JST PRESTO), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) CPSY2023-25 DC2023-25
In recent years, opportunities requiring processing at the IoT edge have been increasing. As a solution, not only conven... [more] CPSY2023-25 DC2023-25
pp.100-105
CPSY, DC, IPSJ-ARC [detail] 2022-07-28
13:30
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic
Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ.), Hayate Okuhara (NUS.), Hideharu Amano (Keio Univ.), Masahiro Iida (Kumamoto Univ.) CPSY2022-8 DC2022-8
In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FP... [more] CPSY2022-8 DC2022-8
pp.41-46
NS, IN
(Joint)
2022-03-10
09:10
Online Online Route Optimization for Traffic Engineering with Flow Re-routing Suppression
Masato Nishiguchi, Takayuki Fujiwara, Satoshi Nakatsukasa, Yuki Takei (NTT) NS2021-122
Traffic Engineering (TE) is an approach to optimize the utilization of network resources for reducing congestion in the ... [more] NS2021-122
pp.1-6
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-10
14:30
Online Online Compression of configuration data in Scalable Logic Module
Souhei Takagi, Naoya Niwa, Yoshiya Shikama, Yosuke Yanai, Hideharu Amano (Keio Univ), Yuya Nakasato, Daiki Amagasaki, Masahiro Iida (Kumamoto Univ) CPSY2021-49 DC2021-83
(To be available after the conference date) [more] CPSY2021-49 DC2021-83
pp.26-31
SS 2021-03-03
13:00
Online Online SS2020-30 (To be available after the conference date) [more] SS2020-30
pp.13-18
KBSE 2019-03-01
14:10
Kyoto Doshisha University Kambaikan Analysis of Learners' Trend Using Visualization Tool for Programming Process
Genki Takayama, Hiroaki Hashiura (NIT), Takahumi Tanaka (TUT), Atsuo Hazeyama (TGU), Hiroshi Takase (NIT) KBSE2018-56
In recent years, Learning Analytics (LA) attracts attention as a big data utilization in education. LA is an attempt to ... [more] KBSE2018-56
pp.13-18
KBSE 2018-05-25
13:50
Tokyo Kikai-Shinko-Kaikan Bldg. A Reproduction Tool for Programming Process Utilizing Fine-Grained Development Records on the Web
Genki Takayama, Hiroaki Hashiura (Nippon Inst. of Tech.), Takafumi Tanaka (Tokyo Univ. of Agriculture and Tech.), Atsuo Hazeyama (Tokyo Gakugei Univ.), Hiroshi Takase (Nippon Inst. of Tech.) KBSE2018-4
In general, software developments are conducted in form of team development. However, developers participated in mainten... [more] KBSE2018-4
pp.13-18
KBSE 2017-11-11
10:30
Shizuoka   A Support Tool for Program Comprehension Utilizing Fine-Grained Development Records
Genki Takayama, Yoshitaka Yamada, Hiroaki Hashiura (NIT), Takafumi Tanaka (TAT), Atsuo Hazeyama (TGU), Hiroshi Takase (NIT) KBSE2017-29
A software development is often put into effect with a project by plural people. However, not always continues to mainta... [more] KBSE2017-29
pp.19-24
MSS, SS 2017-01-26
11:00
Kyoto Kyoto Institute of Technology MSS2016-59 SS2016-38 (To be available after the conference date) [more] MSS2016-59 SS2016-38
pp.13-18
IA 2016-11-09
16:40
Hokkaido Onuma International Seminar Hous Fine-grained traffic control on software router
Takaaki Kuwabara, Daisuke Kotani, Yasuo Okabe (Kyoto Univ.) IA2016-60
We consider fine-grained traffic control on the ingress router in a tree-structured stub network site based on the sourc... [more] IA2016-60
pp.23-28
KBSE 2016-03-04
10:00
Oita   A Programming Learning Support Environment Utilizing Fine-Grained Development Records and Lecture Context
Hiroaki Hashiura (NIT), Kazuki Mori (Shibaura Inst. of Tech.), Takafumi Tanaka, Atsuo Hazeyama (TGU), Seiichi Komiya (NII) KBSE2015-60
In a typical programming exercises that is the backbone of software engineering education, a teacher gives a lecture on ... [more] KBSE2015-60
pp.69-74
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-02
16:20
Nagasaki Nagasaki Kinro Fukushi Kaikan Sleep Control Using Virtual Ground Voltage Detection For Fine-Grain Power Gating
Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2015-57 DC2015-53
This paper describes a sleep control technique using leakage monitor circuit to implement Fine-Grain Power Gating (FGPG)... [more] VLD2015-57 DC2015-53
pp.129-134
KBSE 2015-03-05
13:00
Tokyo The University of Electro-Communications Fine-Grained Analysis of the Class Diagram Creation Process
Takafumi Tanaka (TGU), Hiroaki Hashiura (NIT), Atsuo Hazeyama (TGU), Seiichi Komiya (NII) KBSE2014-54
It is important for software engineers to have modeling skills that understand or abstract essence of problems. Exercise... [more] KBSE2014-54
pp.13-18
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
15:15
Kanagawa Hiyoshi Campus, Keio University A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design
Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2013-130 CPSY2013-101 RECONF2013-84
In order to reduce the power consumption of LSI,
unnecessary parts should be powered off with fine granularity,
and c... [more]
VLD2013-130 CPSY2013-101 RECONF2013-84
pp.167-172
IN, IA
(Joint)
2013-12-19
13:25
Hiroshima Hiroshima City Univ. A power-aware routing-table and its evaluation platform
Takumi Okamoto, Hirotaka Nakano, Kazunari Inoue (Nara National College of Tech.) IA2013-58
While high-performance and large-integration are seamless technical theme for ICT equipment with respect to the continuo... [more] IA2013-58
pp.7-12
SS 2013-05-09
16:20
Kagawa Kagawa University (Saiwaimachi) Detecting Extract Method Refactoring from Repository with Syntactic Information
Kenji Fujiwara, Norihiro Yoshida, Hajimu Iida (NAIST) SS2013-4
Recently, several research have tackled to reveal the effects of refactorings in the software development.
In order to ... [more]
SS2013-4
pp.19-24
VLD 2013-03-06
10:55
Okinawa Okinawa Seinen Kaikan Design and Evalution of Sleep Control Circuit for Fine-grain Power Gating
Yoshihiro Tsurui, Kimiyoshi Usami, Tatsunori Hashida, Tetsuya Muto, Yuki Shimada (Shibaura Inst. of Tech.) VLD2012-155
In order to perform more efficient Fine-grain Power Gating which reduces the leakage power by cutting Power Supply, it i... [more] VLD2012-155
pp.105-110
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-28
13:50
Fukuoka Centennial Hall Kyushu University School of Medicine Control of Fine-Grain Power Gating by Detecting of the Virtual Ground Voltage
Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2012-98 DC2012-64
This paper describes fine-grain control to power gate function units using the charge up phenomenon of the virtual groun... [more] VLD2012-98 DC2012-64
pp.225-230
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-30
11:20
Miyazaki NewWelCity Miyazaki Power-Gating Circuit Scheme for Transient-Glitch Energy Reduction
Yuya Ohta, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-90 DC2011-66
In fine-grain power gating which performs cell-by-cell power gating (PG) , energy overhead consumed at sleep-in and slee... [more] VLD2011-90 DC2011-66
pp.221-226
 Results 1 - 20 of 35  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan