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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS, ICD | 2024-03-02 12:05 |
Okinawa | (Primary: On-site, Secondary: Online) |
A Study on formal verification of GF(2^m) arithmetic circuits including states Kazuho Sakoda (SCU/Kobe Univ.), Yasuyoshi Uemura (SCU), Naofumi Homma (Tohoku Univ.)  VLD2023-140 HWS2023-100 ICD2023-129 |
This paper describes a formal verification method for arithmetic circuits based on computer algebra. Conventional method... [more] | VLD2023-140 HWS2023-100 ICD2023-129 pp.215-220 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-30 10:30 |
Kanagawa | Hiyoshi Campus, Keio University | Error detection using residue signed-digit number arithmetic for arithmetic circuits Yoshitomo Nema, Yuuki Tanaka, Kazuhiro Motegi, Shugang Wei (Gunma Univ) VLD2014-136 CPSY2014-145 RECONF2014-69 |
For error detection of multiply-accumulate operation, a residue error detector can be considered for the VLSI implementa... [more] | VLD2014-136 CPSY2014-145 RECONF2014-69 pp.151-156 |
| DC, CPSY | 2009-04-21 13:50 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | Fast Soft Error Rate Estimation for Circuits Containing Arithmetic Units Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura (Kyushu Univ.) CPSY2009-5 DC2009-5 |
This paper describes soft errors which are errors in LSI that are due to external radiation.The soft error rate (SER) wh... [more] | CPSY2009-5 DC2009-5 pp.25-30 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 15:10 |
Kanagawa | A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application Yoshiaki Satou, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2008-121 CPSY2008-83 RECONF2008-85 |
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] | VLD2008-121 CPSY2008-83 RECONF2008-85 pp.177-182 |
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| RECONF | 2008-05-22 16:05 |
Fukushima | The University of Aizu | A Novel Cluster Structure for Variable Grain Logic Cell Kazuki Inoue, Kazunori Matsuyama, Yoshiaki Satou, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-8 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] | RECONF2008-8 pp.43-48 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2008-03-28 09:50 |
Kagoshima | An Asynchronous IEEE754-standard Single-precision Floating-point Divider for FPGA Masayuki Hiromoto, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) DC2007-105 CPSY2007-101 |
Synchronous design methodology is widely used for today's digital circuits. However, it is difficult to reuse a highly-... [more] | DC2007-105 CPSY2007-101 pp.127-132 |
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| RECONF | 2007-05-17 16:10 |
Ishikawa | Kanazawa Bunka Hall | Performance Evaluation of Variable Grain Logic Cell for Arithmetic Circuits Yoshiaki Satou, Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-7 |
Reconfigurable logic devices are classified into two type of logic block, which are coarse-grain and fine-grain by the b... [more] | RECONF2007-7 pp.37-42 |
| RECONF | 2007-05-18 11:10 |
Ishikawa | Kanazawa Bunka Hall | * Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ.) RECONF2007-14 |
A new architecture of parallel processor is proposed, whose processing element can support various types of operations i... [more] | RECONF2007-14 pp.79-84 |
| NLP | 2006-05-11 14:25 |
Kumamoto | Kumamoto Univ. | Stochastic Computing with Quantization Noise Shaping Naoya Yamamoto, Hisato Fujisaka, Kazuhisa Haeiwa, Takeshi Kamio (Hiroshima City Univ.) |
This paper presents a bit-rate converter and arithmetic circuits for nanoelectronic signal processing systems based on s... [more] | NLP2006-5 pp.21-25 |
| CAS, SIP, VLD | 2005-06-28 13:50 |
Miyagi | Tohoku University | Formal Design of Arithmetic Circuits with Arithmetic Description Language: ARITH Yuki Watanabe, Naofumi Homma, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Tohtech) |
This paper presents a design of parallel multipliers based on arithmetic description language called ARITH. The multipli... [more] | CAS2005-21 VLD2005-32 SIP2005-45 pp.37-42 |
| NLP, CAS | 2004-09-14 13:55 |
Kyoto | Kyoto Univ. | Operators on Multi-Level Delta-Sigma Modulated Signals Kazutoshi Matsuyama, Hisato Fujisaka (Hiroshima City Univ.) |
This paper describes algorithms to process first-order four-level DeltaSigma modulated signals directly without converti... [more] | CAS2004-37 NLP2004-49 pp.55-60 |
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