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Committee Date Time Place Paper Title / Authors Abstract Paper #
MRIS, ITE-MMS 2016-10-20
14:00		 Fukuoka Nishijin Plaza Numerical simulation for inductive detection of magnetic vortex core rotation and polarity switching
Xiaorui Ya, Terumitsu Tanaka, Kimihide Matsuyama (Kyushu Univ.) MR2016-23		 This study describes micromagnetic simulations of vortex core rotations and its polarity switching induced by circularly... [more] MR2016-23
pp.19-22
CPM, ED, SDM 2014-05-28
15:35		 Aichi   First-principles simulation on electron-scattering process in magnetoresistive memory
Masaaki Araidai (Nagoya Univ.), Takahiro Yamamoto (Tokyo Univ. of Sci.), Kenji Shiraishi (Nagoya Univ.) ED2014-27 CPM2014-10 SDM2014-25		 Magnetoresistance memory is expected as emerging memory device due to the desired functions such as non-volatility, fast... [more] ED2014-27 CPM2014-10 SDM2014-25
pp.47-50
SDM, ED 2009-06-24
15:00		 Overseas Haeundae Grand Hotel, Busan, Korea Transient characteristic of fabricated Magnetic Tunnel Junction (MTJ) programmed with CMOS circuit
Masashi Kamiyanagi, Fumitaka Iga, Shoji Ikeda (Tohoku Univ.), Katsuya Miura (Tohoku Univ./Hitachi), Jun Hayakawa (Hitachi), Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ED2009-52 SDM2009-47		 In this paper, it is shown that our fabricated MTJ of 60x180${\rm nm^2}$, which is connected to the MOSFET in series by ... [more] ED2009-52 SDM2009-47
pp.9-12
SDM, ED 2009-06-24
15:15		 Overseas Haeundae Grand Hotel, Busan, Korea Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-end Metal Line of CMOS Circuits
Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda (Tohoku Univ.), Katsuya Miura (Tohoku Univ./Hitachi), Jun Hayakawa (Hitachi), Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ED2009-53 SDM2009-48		 In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrat... [more] ED2009-53 SDM2009-48
pp.13-16
ICD 2005-04-15
10:30		 Fukuoka   A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture
Takaharu Tsuji (Renesas Technorogy), Hiroaki Tanizaki (Renesas Device Design), Masatoshi Ishikawa, Jun Otani, Yuichiro Yamaguchi, Shuichi Ueno, Tsukasa Oishi, Hideto Hidaka (Renesas Technorogy) 		A 1Mbit MRAM with a 0.81um2 1-Transistor 1-Magnetic Tunnel Junction (1T-1MTJ) cell using 0.13um 4LM logic technology has... [more] ICD2005-13
pp.1-6
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