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 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]		 2018-12-06
13:00		 Hiroshima Satellite Campus Hiroshima Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-56 DC2018-42		 3D die-stacking technique using TSVs has gained much attention as a new integration method of IC.
However, faulty TSVs ... [more]		 VLD2018-56 DC2018-42
pp.119-124
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]		 2018-12-06
13:50		 Hiroshima Satellite Campus Hiroshima Study on the Applicability of ATPG Pattern for DFT Circuit
Kohki Taniguchi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-58 DC2018-44		 With high integration of IC, small delay faults have occurred as the cause of a circuit failure. As a design-for-testabi... [more] VLD2018-58 DC2018-44
pp.131-136
DC 2018-02-20
10:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2017-79		 TSV attracts attention as a new implementation method of interconnects between dies in 3DICs.
However, faulty TSVs may ... [more]		 DC2017-79
pp.13-18
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]		 2016-11-30
09:25		 Osaka Ritsumeikan University, Osaka Ibaraki Campus Design of TDC Embedded in Scan FFs for Testing Small Delay Faults
Shingo Kawatsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2016-62 DC2016-56		 With improvement of semiconductor manufacturing process, small delay becomes more important cause of timing failures.
... [more]		 VLD2016-62 DC2016-56
pp.105-110
DC, CPSY 2013-04-26
16:40		 Tokyo   On-Chip Delay Measurement Using Adjacent Test Architecture
Kentaroh Katoh (TNCT) CPSY2013-8 DC2013-8		 This paper proposes an on-chip delay measurement using adjacent test architecture with TDC (Time to Digital Converter). ... [more] CPSY2013-8 DC2013-8
pp.43-48
DC 2012-06-22
13:00		 Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg An evaluation of a don't care filling method to improve fault sensitization coverage
Ryosuke Wakasugi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyusyu Univ) DC2012-9		 A single stuck-at fault model and a transition fault model have been widely used to generate test patterns for VLSIs. Ho... [more] DC2012-9
pp.1-6
 Results 1 - 6 of 6  /   
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