Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, HWS, ICD |
2024-03-02 12:05 |
Okinawa |
(Primary: On-site, Secondary: Online) |
A Study on formal verification of GF(2^m) arithmetic circuits including states Kazuho Sakoda (SCU/Kobe Univ.), Yasuyoshi Uemura (SCU), Naofumi Homma (Tohoku Univ.) VLD2023-140 HWS2023-100 ICD2023-129 |
This paper describes a formal verification method for arithmetic circuits based on computer algebra. Conventional method... [more] |
VLD2023-140 HWS2023-100 ICD2023-129 pp.215-220 |
KBSE |
2023-03-17 14:35 |
Hiroshima |
JMS ASTERPLAZA (Primary: On-site, Secondary: Online) |
Development of Co-Analysis Support Tool by Linking Simulink and SMT Solver Engielista Anak Norman, Yoshikazu Ueda (Ibaraki Univ.) KBSE2022-67 |
In order to target various models in co-analysis, it is necessary to be able to select the SMT solver according to the c... [more] |
KBSE2022-67 pp.79-84 |
ITS, IEE-ITS |
2021-03-15 15:05 |
Online |
Online |
Model Checking-Based Verification of Token-Based Traffic Control for Roundabouts Tatsuhiro Tsuchiya (Osaka Univ.), Satoshi Otsuka (Hitachi) ITS2020-43 |
This paper reports the results of model checking-based verification of a traffic control mechanism for roundabouts. This... [more] |
ITS2020-43 pp.41-44 |
NS, ICM, CQ, NV (Joint) |
2020-11-27 11:45 |
Online |
Online |
A Proposal of Framework for Authentication Systems and Verification Method Motoshi Horii, Toshihiro Shimizu (Fujitsu Lab.), Satoshi Imai (Fujitsu) CQ2020-58 |
With the digitization of various procedures, various security incidents have been occurring frequently. To prevent the o... [more] |
CQ2020-58 pp.62-65 |
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] |
2019-07-23 13:10 |
Kochi |
Kochi University of Technology |
A Formal Approach to Verifying Trojan-freeness of Cryptographic Circuits Based on Galois-Field Arithmetic Akira Ito, Rei Ueno, Naofumi Homma (Tohoku Univ.) ISEC2019-26 SITE2019-20 BioX2019-18 HWS2019-21 ICSS2019-24 EMM2019-29 |
This paper proposes a formal method for verifying whether Hardware Trojan (HT) exists or not (i.e., HT-freeness) in cryp... [more] |
ISEC2019-26 SITE2019-20 BioX2019-18 HWS2019-21 ICSS2019-24 EMM2019-29 pp.133-138 |
SS |
2019-03-04 17:10 |
Okinawa |
|
Formal STAMP Modelling toward Safety Verification of Hybrid Systems Mitsuaki Tsuji, Toshinori Takai (NAIST), Masafumi Katahira, Naoki Ishihama (JAXA), Kazuki Kakimoto, Hajimu Iida (NAIST) SS2018-67 |
Safety-critical systems, for example, autonomous vehicles and space systems, are required to be safe and reliable. Recen... [more] |
SS2018-67 pp.91-96 |
ICSS, IA |
2018-06-26 10:45 |
Ehime |
Ehime University |
[Invited Talk]
Security Analysis with Formal Methods Naoto Yanai (Osaka Univ.) IA2018-12 ICSS2018-12 |
For security analysis of information security researches, a method with a formal proof has attracted attention in recent... [more] |
IA2018-12 ICSS2018-12 pp.73-75 |
KBSE, SS, IPSJ-SE [detail] |
2015-07-24 09:00 |
Hokkaido |
|
A Study on a Formal Verification Method Using Atelier-B Ryota Yamamoto, Shuichiro Yamamoto (Nagoya Univ.) SS2015-29 KBSE2015-22 |
In this paper, we try to evaluate a formal verification method using Atelier-B, a delopment tool for B-method. To enhanc... [more] |
SS2015-29 KBSE2015-22 pp.143-148 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 10:45 |
Oita |
B-ConPlaza |
A hardware description method and sematics providing a timing constrant Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) VLD2014-82 DC2014-36 |
Formal verification methods are wide-spreading due to its mathmatical rigorousaspect, although they limited to synchroun... [more] |
VLD2014-82 DC2014-36 pp.81-86 |
RECONF |
2014-09-19 14:40 |
Hiroshima |
|
Formal Verification System of Multi-clock Synchronous Circuits on Multimodal Logic Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-33 |
Regardless of wide using of a formal verification methods, almost all of the methods limited to single-clock synchrounou... [more] |
RECONF2014-33 pp.93-98 |
SS |
2014-03-11 10:30 |
Okinawa |
Tenbusu Naha |
Generation and Verification of Decision Table using SAT Solver Shinji Itoh, Naoto Sato, Hidetaka Kondoh, Kunihiko Miyazaki, Hiroki Mori, Makoto Kimura, Kiyoshi Yamaguchi (Hitachi) SS2013-73 |
Use of a decision table is an effective method to prevent defects of combination patterns of conditions. However, it is ... [more] |
SS2013-73 pp.7-11 |
VLD |
2014-03-05 15:45 |
Okinawa |
Okinawa Seinen Kaikan |
A Case Study of Symbolic Model Checking for Verilog-HDL Hardware Design Tomoyuki Yokogawa, Daichi Higashiyama (Okayama Pref. Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Yoichiro Sato, Kazutami Arimoto (Okayama Pref. Univ.) VLD2013-166 |
In this paper, we show a case study where a design of 8bit microcomputer M8R, which is described by Verilog-HDL, is veri... [more] |
VLD2013-166 pp.177-182 |
SS, MSS |
2014-01-31 09:55 |
Aichi |
|
Bounded model checking based in SMT for CISC embedded assembly programs Atsushi Takeshita, Junpei Kobashi, Satoshi Yamane (Kanazawa Univ.) MSS2013-62 SS2013-59 |
In this paper,we describe the method of verification by bounded model checking based in SMT using Code Block for embedde... [more] |
MSS2013-62 SS2013-59 pp.65-70 |
KBSE |
2012-11-22 11:25 |
Ishikawa |
Kanazawa University |
SMT-based Bounded Model Checking for Assembly program Junpei Kobashi, Atsushi Takeshita, Satoshi Yamane (Kanazawa Univ.) KBSE2012-41 |
In this paper, we state property verification by Bounded Model Checking using SMT solver for register level model of ass... [more] |
KBSE2012-41 pp.19-24 |
MSS |
2012-03-09 13:00 |
Tokyo |
JAIST Tokyo Satellite |
Formal Verification of a Telephone System with a Concierge Server Keito Kurono, Aya Maeda, Yoshinobu Kawabe (Aichi Inst. Tech.) MSS2011-84 |
To avoid becoming a victim of phone fraud, it is important to check whether a caller is a scammer or not.
Yamamoto et.a... [more] |
MSS2011-84 pp.61-66 |
KBSE |
2011-11-11 13:20 |
Nagano |
Shinshu Univ. |
A Formal Verification Method by Transforming UML Models of Web Applications Takahiko Ohsuga (Waseda Univ.), Kouichi Ono (IBM), Yoshiaki Fukazawa (Waseda Univ.) KBSE2011-49 |
Model checking techniques are being applied to application software for formal verifications. Regarded as results of dev... [more] |
KBSE2011-49 pp.79-84 |
SS |
2011-10-28 11:45 |
Ishikawa |
JAIST |
Towards a formal verification of interrupts in TOPPERS/ASP by the separation logic Takashi Nakashima, Shoji Yuen (Nagoya Univ.) SS2011-37 |
We give a formal verification of a fragment of ARM assembly code in TOPPERS/ASP to handle interrupts using the separatio... [more] |
SS2011-37 pp.61-66 |
SIP, ICD, IE, IPSJ-SLDM |
2005-10-21 15:30 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Monitor Generation Method for Formal Monitor-based Verification Considering Input Constraints Yosuke Kakiuchi (Osaka Univ.), Akira Kitajima (Osaka Electro-Communication Univ.), Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) |
In order to verify hardware module interfaces, various verification methods have been proposed. This paper focuses on fo... [more] |
SIP2005-127 ICD2005-146 IE2005-91 pp.73-78 |