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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, IPSJ-SLDM | 2014-05-29 13:25 |
Fukuoka | Kitakyushu International Conference Center | Error Tolerance of Dual Pipeline Self Synchronous Circuits Sai Denki, Makoto Ikeda (Univ. of Tokyo)  VLD2014-7 |
Soft errors caused by collision of neutrons in cosmic rays and atoms in LSIs in electronic equipment are believed to be ... [more] | VLD2014-7 pp.33-38 |
| VLD, IPSJ-SLDM | 2014-05-29 13:50 |
Fukuoka | Kitakyushu International Conference Center | SOTB 65nm CMOS Design of Gate-Level Dual Pipeline Self-Synchronous Wallace Tree Multiplier Masato Tamura, Makoto Ikeda (Univ. of Tokyo) VLD2014-8 |
Thanks to recent advances, the size of transistor shrinks and degree of integration becomes high. Butbecause of that adv... [more] | VLD2014-8 pp.39-44 |
| VLD | 2014-03-05 16:10 |
Okinawa | Okinawa Seinen Kaikan | Implementation of General-Synchronous Circuits into FPGA using Multi-Domain Clock Skew Scheduling Tatsuya Masui, Yukihide Kohira (Univ. of Aizu) VLD2013-167 |
Recently, instead of implementation into ASIC, implementation into FPGA is used in many fields. However, in general, cir... [more] | VLD2013-167 pp.183-188 |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
An ultra-low-voltage power-supply monitor circuit for wireless-powered microparticle manipulation system Ji Cui, Hirosuke Iwasaki, Yoshiaki Dei, Toshimasa Matsuoka (Osaka Univ.) ICD2013-105 |
This paper presents a voltage sensor (VS) circuit to monitor the supply voltage induced on wireless-pow-ered micropartic... [more] | ICD2013-105 pp.15-18 |
| ED, MW | 2014-01-16 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Novel Millimeter-wave PLL Synthesizer with Cascaded Phase Detectors Hiroshi Matsumura, Yoichi Kawano, Masaru Sato, Takenori Ohshima, Toshihiro Shimura, Toshihide Suzuki, Yoji Ohashi (Fujitsu), Naoki Hara (Fujitsu Lab.) ED2013-114 MW2013-179 |
We present a novel millimeter-wave PLL architecture with cascaded phase detectors. It realizes low phase noise and low s... [more] | ED2013-114 MW2013-179 pp.25-28 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-07 11:20 |
Aomori | Construction of an Automatic Design Flow for Dual Pipelined Self-Synchronous Circuit Atsushi Ito, Makoto Ikeda (Univ. of Tokyo) VLD2013-48 ICD2013-72 IE2013-48 |
With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inhe... [more] | VLD2013-48 ICD2013-72 IE2013-48 pp.13-18 |
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| VLD | 2013-03-06 13:40 |
Okinawa | Okinawa Seinen Kaikan | A Delay Control Circuit with Channel Length Decomposition and Its Application Yuichi Toyota, Yuki Nakashima, Toru Fujimura, Shigetoshi Nakatake (Univ of Kitakyushu) VLD2012-158 |
In recent years, as the progress of the semiconductor manufacturing, the variations of circuit performance due to device... [more] | VLD2012-158 pp.123-128 |
| ICD | 2012-12-17 15:55 |
Tokyo | Tokyo Tech Front | [Poster Presentation]
A New Approach of the Analysis of the ISF in Oscillators with a Closed-Loop Control Junki Mizuno, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) ICD2012-97 |
The derivation of the impulse sensitivity function (ISF) of oscillators are widely used for the evaluation of the phase ... [more] | ICD2012-97 pp.37-40 |
| OCS | 2012-07-26 14:05 |
Shizuoka | 32 RZ/QAM coherent optical transmission employing an RZ-CW conversion technique Keisuke Kasai, David Odeke Otuya, Masato Yoshida, Toshihiko Hirooka, Masataka Nakazawa (Tohoku Univ.) OCS2012-23 |
Coherent optical time division multiplexing (OTDM) transmission with a multi-level modulation format has attracted a lot... [more] | OCS2012-23 pp.13-18 |
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| EMCJ, ITE-BCT | 2012-03-16 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Study on Phase Comparator Sesitivity for Low Phase-Noise PLL Hideyasu Hobara, Yoshiki Kayano, Hiroshi Inoue (Akita Univ.) EMCJ2011-141 |
An UWB RF system can be used in the area of signal processing. The phase-noise of output voltage of the oscillator with ... [more] | EMCJ2011-141 pp.67-72 |
| DC | 2012-02-13 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Generation Method for Synchronously Designed QDI Circuits Koki Uchida, Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST) DC2011-83 |
Quasi-Delay-Insensitive(QDI) design has been attracting attention as one of the practical techniques for implementation ... [more] | DC2011-83 pp.43-48 |
| ICD | 2011-12-15 16:10 |
Osaka | [Poster Presentation]
Simulation and Analysis of the Interference Noise between PLL circuits. Ken Maruhashi, Junki Mizuno, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (Osaka Inst. Tech.), Yoshio Matsuda (Kanazawa Univ.) ICD2011-110 |
When the multiple PLL circuits are laid out on a single IC chip, the influence of the interference between PLL circuits ... [more] | ICD2011-110 pp.57-58 |
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| CAS, NLP | 2011-10-21 15:30 |
Shizuoka | Shizuoka Univ. | The 1/f Noise Generation in Charge-Pump Phase-Locked Loops
-- Simulation Study by LT-SPICE -- Kyosuke Kato, Yuhei Chiba, Isao Imai, Tetsuro Endo (Meiji Univ.) CAS2011-58 NLP2011-85 |
In this report we perform simulation study of a charge-pump phase-locked loop (CP-PLL) with frequency-modulated input si... [more] | CAS2011-58 NLP2011-85 pp.147-152 |
| OCS | 2011-07-12 15:50 |
Osaka | Osaka Univ. Nakanoshima Center | Frequency Division Multiplexing 64 QAM-OFDM (420Gb /s) transmission over 160 km Tatsunori Omiya, Kazushi Toyoda, Keisuke Kasai, Masato Yoshida, Masataka Nakazawa (Tohoku Univ.) OCS2011-43 |
We have demonstrated 64QAM-OFDM coherent optical transmission with a C2H2 frequency-stabilized fiber laser and an optica... [more] | OCS2011-43 pp.93-98 |
| OCS, NS, PN (Joint) |
2010-06-24 10:45 |
Akita | Akita University | Single-channel 400 Gbit/s, OTDM-32 RZ/QAM coherent transmission over 225 km Keisuke Kasai, Tatsunori Omiya, Pengyu Guan, Masato Yoshida, Toshihiko Hirooka, Masataka Nakazawa (Tohoku Univ.) OCS2010-11 |
Coherent optical time division multiplexing (OTDM) transmission with a multi-level modulation format based on digital si... [more] | OCS2010-11 pp.1-6 |
| OCS, NS, PN (Joint) |
2010-06-25 09:20 |
Akita | Akita University | High Sensitive Clock Extraction for a 160Gbit/s OTDM Signal Shigehiro Takasaka, Yu Mimura, Takeshi Yagi (Furukawa Electric) OCS2010-18 |
We have demonstrated a high sensitive clock recovery using an optoelectronic phase-locked loop (PLL). High trans-impedan... [more] | OCS2010-18 pp.43-47 |
| VLD, IPSJ-SLDM | 2010-05-20 13:05 |
Fukuoka | Kitakyushu International Conference Center | A Wide-Range Clock Synchronizer with Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS Control Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu (Hitachi), Yoshihiko Yasu, Koichiro Ishibashi (Renesas) VLD2010-7 |
A ``wide-range voltage-and-frequency clock synchronizer'' for maintaining synchronization during voltage-scaling transit... [more] | VLD2010-7 pp.67-72 |
| VLD | 2010-03-11 15:00 |
Okinawa | Fast Estimation Method of Peak Power considered Input Vector and Inner State of a Circuit Nobuyoshi Takahashi (Tokyo Inst. of Tech.), Yoichi Tomioka (Tokyo Univ. of Agriculture and Tech.), Yukihide Kohira (The Univ. of Aizu), Atsushi Takahashi (Osaka Univ.) VLD2009-115 |
The peak power of a clock synchronous circuit is requested to be small to reduce the influence on circuit performance an... [more] | VLD2009-115 pp.97-102 |
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| VLD | 2009-03-11 16:15 |
Okinawa | A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits Shuhei Tani, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-135 |
In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily si... [more] | VLD2008-135 pp.53-58 |
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| VLD, ICD | 2008-03-07 10:05 |
Okinawa | TiRuRu | A Self-timed Processor with Dynamic Voltage Scaling Taku Sogabe, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo) VLD2007-158 ICD2007-181 |
As PVT variations get larger, synchronous circuits are getting less reliable and timing margins are getting larger. Self... [more] | VLD2007-158 ICD2007-181 pp.13-18 |
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