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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| EMCJ | 2023-11-24 16:15 |
Tokyo | Kikai-Shinko-Kaikan (Primary: On-site, Secondary: Online) |
Fundamental Study on the Influence of Frequency Multiplication Ratio of Phase-Locked loop on Fault Injection into Cryptographic Modules Hikaru Nishiyama, Daisuke Fujimoto, Yuichi Hayashi (NAIST)  EMCJ2023-80 |
(To be available after the conference date) [more] | EMCJ2023-80 pp.46-50 |
| ICD, HWS | 2023-10-31 13:55 |
Mie | (Primary: On-site, Secondary: Online) |
Fundamental Study on Fault Analysis Based on Glitch Injection into Phase-Locked Loop Hikaru Nishiyama, Daisuke Fujimoto, Yuichi Hayashi (NAIST) HWS2023-55 ICD2023-34 |
(To be available after the conference date) [more] | HWS2023-55 ICD2023-34 pp.5-9 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 09:55 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Design of Digital Phase-Locked Loop Circuit based on 3rd-Order MASH ΔΣ FDC for Low In-Band Phase Noise Ryoga Iwashita, Zule Xu, Masaru Osada, Ryoya Shibata, Yo Kumano, Tetsuya Iizuka (UTokyo) VLD2022-43 ICD2022-60 DC2022-59 RECONF2022-66 |
$DeltaSigma$ frequency-to-digital converter based phase locked loops (FDC-PLLs) can reduce its quantization noise at low... [more] | VLD2022-43 ICD2022-60 DC2022-59 RECONF2022-66 pp.138-143 |
| NLP | 2021-12-17 13:05 |
Oita | J:COM Horuto Hall OITA | A Study on On-off Intermittency and Its Transient Dimension in Coupled Phase-locked Loops with Delay Tetsushi Saburi, Takashi Hikihara (Kyoto Univ.) NLP2021-48 |
When we take into account the length of wiring and the delay time attributed to the operation process, a phase-locked lo... [more] | NLP2021-48 pp.26-29 |
| ICD, CPSY, CAS | 2018-12-23 09:30 |
Okinawa | [Poster Presentation]
Evaluation of performance of 5GHz PLL with high-frequency injection pulses Yuuki Kojima, Takao Kihara, Tsutomu Yoshimura (OIT) CAS2018-97 ICD2018-81 CPSY2018-63 |
Recent years, The high-frequency and the low-jitter clock generation is required due to speeding up of the communication... [more] | CAS2018-97 ICD2018-81 CPSY2018-63 pp.81-82 |
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| ICD, CPSY, CAS | 2018-12-23 09:30 |
Okinawa | [Poster Presentation]
Evaluation of jitter performance with external- and self-injection in PLL circuit Tatsuya Okafuji, Kazuki Miyao, Takao Kihara, Tsutomu Yoshimura (OIT) CAS2018-100 ICD2018-84 CPSY2018-66 |
In recent years, high-speed clock with high precision is required as communication speed increases. We have confirmed th... [more] | CAS2018-100 ICD2018-84 CPSY2018-66 pp.91-93 |
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| VLD, HWS (Joint) |
2018-03-01 13:00 |
Okinawa | Okinawa Seinen Kaikan | An Evaluation of Graph Reduction Technique for Delay Insertion of General-Synchronous Circuit Yuki Arai, Shuji Tsukiyama (Chuo Univ.) VLD2017-110 |
In general-synchronous framework, the clock signal is distributed to each register in optimal individual timing, so that... [more] | VLD2017-110 pp.127-132 |
| OPE, OCS, OFT (Joint) [detail] |
2018-02-16 10:40 |
Okinawa | Okinawa Prefectural Museum | Pump Phase-Locked to PDM Phase-Conjugated Twin Waves by using Phase Modulation in Optical Parametric Phase-Sensitive Amplifier Repeaters Ikuya Nagatomi, Kouhei Aga, Takumi Okabe, Wataru Nakanishi, Yasuhiro Okamura (Tokushima Univ.), Takeshi Umeki, Ryoichi Kasahara (NTT), Atushi Takada (Tokushima Univ.) OCS2017-88 OPE2017-181 |
Pump phase-locked to PDM phase-conjugated twin waves (PDM-PCTWs) in optical parametric phase-sensitive amplifier repeate... [more] | OCS2017-88 OPE2017-181 pp.45-48(OCS), pp.63-66(OPE) |
| NLP, CAS | 2017-10-05 15:50 |
Niigata | Machinaka Campus Nagaoka | [Invited Talk]
Exploring optimality in nonliear problems
-- Applications to design methodology of injection-locking circuits and new vibration engineering -- Hisa-Aki Tanaka, Masaki Nakagawa (UEC), Hiroo Sekiya (Chiba Univ.) CAS2017-30 NLP2017-55 |
We have been enabling optimizing injection-locking phenomena, in collaboration with research groups in U.S. for these se... [more] | CAS2017-30 NLP2017-55 pp.35-40 |
| AP | 2017-03-17 11:20 |
Iwate | Iwate Univ. | Study of measurement accuracy in precise propagation measurement using the Digital Terrestrial Television Broadcasting signal Hiroki Ohta (NICT) AP2016-194 |
We are studying precise propagation measurement using terrestrial digital broadcasting and have been studying the influe... [more] | AP2016-194 pp.93-98 |
| MSS, CAS, IPSJ-AL [detail] | 2016-11-25 12:55 |
Hyogo | Kobe Institute of Computing | Formal Description of Synchronization by Functional Definition of Synchronous Circuits Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) CAS2016-73 MSS2016-53 |
Synchronous circuits are usually defined as D-Flipflop (D-FF) synchronized circuits, but it is doubtful that D-FF comple... [more] | CAS2016-73 MSS2016-53 pp.99-104 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-01 13:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit Masato Tamura, Makoto Ikeda (Univ. of Tokyo) VLD2015-39 DC2015-35 |
In this paper, we investigated the implementation method of elliptic curve digital signature algorithm using self-synchr... [more] | VLD2015-39 DC2015-35 pp.7-12 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 09:20 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems Kohta Itani, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2015-60 DC2015-56 |
This report is intended to discuss the scheduling problem in high-level synthesis~(HLS) for four-phase dual-rail asynchr... [more] | VLD2015-60 DC2015-56 pp.147-152 |
| NLP | 2015-11-01 10:35 |
Okinawa | Nobumoto Ohama Memorial Hall | Electronic Circuit Experiments of Double Covering Bifurcation of 2-Torus Quasi-Periodic Solution in Phase-Locked Loop Circuit Kyohei Kamiyama, Tetsuro Endo (Meiji Univ.), Isao Imai (AIPHONE) NLP2015-118 |
Double covering bifurcation of 2-torus quasi-periodic solution can be observed in our electronic circuit experiment of... [more] |
NLP2015-118 pp.63-68 |
| NLP, CCS | 2015-06-12 12:45 |
Tokyo | Waseda Univerisity | A Method for Obtaining Saddle Type Quasi-Periodic Solution of 2-Torus Double Covering Bifurcation in Phase Locked Loop Equation Kyohei Kamiyama (Meiji Univ.), Motomasa Komuro (Teikyo Univ. of Sci.), Tetsuro Endo (Meiji Univ.) NLP2015-59 CCS2015-21 |
We developed obtaining method for the saddle quasi-periodic solution in continuous and discrete time dynamical system ... [more] |
NLP2015-59 CCS2015-21 pp.121-124 |
| VLD | 2015-03-04 10:20 |
Okinawa | Okinawa Seinen Kaikan | Optimization of sequential circuit in gate-level pipelined self-synchronous circuit design Atsushi Ito, Makoto Ikeda (The Univ. of Tokyo) VLD2014-177 |
With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inhe... [more] | VLD2014-177 pp.135-140 |
| SDM, EID | 2014-12-12 14:00 |
Kyoto | Kyoto University | Characterization of Synchronous and Asynchronous Circuits using poly-Si TFTs Yosuke Nagase (Ryukoku Univ.), Tokiyoshi Matsuda, Mutsumi Kimura (Osaka Univ.), Taketoshi Matsumoto, Hikaru Kobayashi (Ryukoku Univ.) EID2014-25 SDM2014-120 |
We have evaluated multiple-input NAND circuits using polycrystalline silicon thin-film transistors and found that the ou... [more] | EID2014-25 SDM2014-120 pp.61-65 |
| MRIS, ITE-MMS | 2014-12-11 15:05 |
Ehime | Ehime Univ. | A study on PLL design for high recording density tape system Atsushi Musha (FUJIFILM/Ehime Univ.), Osamu Shimizu (FUJIFILM), Yasuaki Nakamura, Yoshihiro Okamoto (Ehime Univ.) MR2014-32 |
Timing recovery method for high density tape storage system is studied. Since tape system suffers from large speed varia... [more] | MR2014-32 pp.23-27 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 10:45 |
Oita | B-ConPlaza | A hardware description method and sematics providing a timing constrant Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) VLD2014-82 DC2014-36 |
Formal verification methods are wide-spreading due to its mathmatical rigorousaspect, although they limited to synchroun... [more] | VLD2014-82 DC2014-36 pp.81-86 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:05 |
Oita | B-ConPlaza | Optimization for gate-level pipelined self-synchrnous circuit Atsushi Ito, Makoto Ikeda (Univ. of Tokyo) VLD2014-107 DC2014-61 |
With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inhe... [more] | VLD2014-107 DC2014-61 pp.233-238 |
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