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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2011-09-27 11:00 |
Aichi | Nagoya Univ. | Performance Evaluation of Power Monitoring Programs on Reconfigurable Processor DS-HIE Kyohei Tao, Takatoshi Tamaoki, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)  RECONF2011-36 |
In recently years, a smart grid has been emerging as a new power network. As the smart grid needs a smart meter, a sma... [more] |
RECONF2011-36 pp.81-86 |
| RECONF | 2010-09-16 13:50 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | A Consideration of Reconfigurable Processor for RSA Cryptography Takatoshi Tamaoki, Kazuya Tanigawa, Tetsuo Hironaka (hcu) RECONF2010-22 |
Encrypting and decrypting RSA require many exponentiation calculations, and modulo calculation with bit-with wider than... [more] |
RECONF2010-22 pp.25-30 |
| RECONF | 2010-09-16 15:25 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Evaluation of Multiple-Precision Floating-Point Accelerator HP-DSFP through Applications. Yuki Yoshioka, Tomoyuki Kawamoto, Taiga Ban, Kazuya Tanigawa, Tetsuo Hironaka (HCU) RECONF2010-25 |
In recent years, many kinds of scientific application programs, such as Fluid analysis, Feynman loop integrals and conju... [more] | RECONF2010-25 pp.43-48 |
| RECONF | 2009-09-18 09:00 |
Tochigi | Utsunomiya Univ. | A Proposal for a Method to Generate Optimized Dataflow for Reconfigurable Processor DS-HIE Based on Bit Serial Operation Yasuhiro Nishinaga, Ken'ichi Umeda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2009-28 |
Our laboratory has developed a reconfigurable processor DS-HIE based on bit-serial operation. The DS-HIE processor achie... [more] | RECONF2009-28 pp.55-60 |
| RECONF | 2009-09-18 09:25 |
Tochigi | Utsunomiya Univ. | Consideration of Data Transfer Unit in Reconfigurable Processor DS-HIE Ken'ichi Umeda, Yasuhiro Nishinaga, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ) RECONF2009-29 |
We have developed reconfigurable processor DS-HIE based on bit-serial operation. The merit of bit-serial operation is th... [more] | RECONF2009-29 pp.61-66 |
| RECONF | 2009-09-18 15:00 |
Tochigi | Utsunomiya Univ. | A study of an Implementation Method of a Mathematical Function in Reconfigurable Accelerator with High-Precision Floating Point Arithmetic Yuki Yoshioka, Tomoyuki Kawamoto, Taiga Ban, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ) RECONF2009-39 |
In recent years, many kinds of scientific application programs require high-precision floating-point operations. For i... [more] |
RECONF2009-39 pp.119-124 |
| RECONF | 2009-05-14 13:00 |
Fukui | Performance Evaluation of Reconfigurable Processor Hy-DiSC based on MeP Hardware Extension Ken'ichi Umeda, Takuro Uchida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ) RECONF2009-1 |
We have developed the reconfigurable processor Hy-DiSC for stream processing. Hy-DiSC processor consists of MeP and DS-H... [more] | RECONF2009-1 pp.1-6 |
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| RECONF | 2008-05-22 14:50 |
Fukushima | The University of Aizu | Development of Compiler for Dynamic Reconfigurable Architecture DS-HIE which Adopts Digit-serial Computation Yasuhiro Nishinaga, Takuro Uchida, Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2008-5 |
In our laboratory, to realize speedup of the streaming processing for small scale systems such as embeded systems, we ha... [more] | RECONF2008-5 pp.25-30 |
| RECONF | 2007-05-18 11:10 |
Ishikawa | Kanazawa Bunka Hall | * Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ.) RECONF2007-14 |
A new architecture of parallel processor is proposed, whose processing element can support various types of operations i... [more] | RECONF2007-14 pp.79-84 |
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