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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IE, SIP, ICD, VLD, IPSJ-SLDM [detail] | 2012-10-19 13:00 |
Iwate | Hotel Ruiz | Accelerator Architecture for Multi Scale Filter Operation Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)  VLD2012-51 SIP2012-73 ICD2012-68 IE2012-75 |
Image recognition processing includes a number of filter operations which dominate the total execution time. Exploiting... [more] |
VLD2012-51 SIP2012-73 ICD2012-68 IE2012-75 pp.59-64 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:20 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Three-Dimensional Accelerator Architecture for Image Recognition Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) SIP2011-63 ICD2011-66 IE2011-62 |
Image recognition used widely in several areas needs high-performance and low power processor. Accelerator is an effecti... [more] | SIP2011-63 ICD2011-66 IE2011-62 pp.7-12 |
| VLD | 2011-03-03 14:10 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | A Circuit Synthesis for Dynamic Reconfigurable Processor Nobuyuki Araki, Takashi Kambe (Kinki Univ.) VLD2010-131 |
Dynamic reconfiguraible processors can implement large-scale and complicated circuits by changing its configurations dur... [more] | VLD2010-131 pp.87-92 |
| RECONF | 2009-09-18 09:50 |
Tochigi | Utsunomiya Univ. | Comparison and Evaluation of Application Implementation Methods for Dynamically Reconfigurable Processor DAPDNA-2 Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ) RECONF2009-30 |
Design tools are essential to implement applications on dynamically reconfigurable hardware efficiently, therefore to un... [more] | RECONF2009-30 pp.67-72 |
| MSS | 2009-06-03 14:25 |
Osaka | Setsunan University, Osaka Center | Model checking of cooperated systems consisting of CPU and DRP Shota Minami, Shingo Takinai, Satoshi Sekoguchi, Satoshi Yamane (Kanazawa Univ.) CST2009-3 |
In this paper, we propose formal verification for cooperated systems consisting of CPU and DRP. First, we specify CPU as... [more] | CST2009-3 pp.13-18 |
| RECONF | 2008-09-25 13:30 |
Okayama | Okayama Univ. | Implementation of JPEG Encoder on Dynamically Reconfigurable Processor and its Evaluation Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ) RECONF2008-24 |
Recently, dynamically reconfigurable hardware has been attracted, the research becomes active, and quantitative evaluati... [more] | RECONF2008-24 pp.7-12 |
| VLD, CAS, SIP | 2008-06-26 13:50 |
Hokkaido | Hokkaido Univ. | Evaluation of Dynamically Reconfigurable Processor in Implementing Sequential Execution of Image Processing Ryosuke Watanabe, Koki Abe (UEC) CAS2008-11 VLD2008-24 SIP2008-45 |
Recently, image applications are frequently executed using mobile devises, where executions with high speed at low cost ... [more] | CAS2008-11 VLD2008-24 SIP2008-45 pp.57-62 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2008-03-28 14:45 |
Kagoshima | A Context Assignment Algorithm for Real-time Tasks on Dynamically Reconfigurable Processor with Reconfigurable Overhead Keisuke Nishi (Osaka Univ.), Tomoya Kitani (NAIST), Akio Nakata (Hiroshima City Univ.), Teruo Higashino (Osaka Univ.) DC2007-114 CPSY2007-110 |
(To be available after the conference date) [more] | DC2007-114 CPSY2007-110 pp.179-184 |
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| VLD, ICD | 2008-03-07 15:45 |
Okinawa | TiRuRu | A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Processor Atsurou Yoshida, Yuji Higashi, Wataru Miyazaki, Teruhito Tanaka, Takashi Kambe (Kinki University) VLD2007-167 ICD2007-190 |
Reed-Solomon Decoder can correct continues error and it has been a popular technology for various devices such as commu... [more] |
VLD2007-167 ICD2007-190 pp.65-68 |
| ICD, SDM | 2007-08-23 09:20 |
Hokkaido | Kitami Institute of Technology | Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding Hiroaki Shikano (Hitachi/./Waseda Univ.), Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama (Hitachi), Toshihiko Odaka (Hitachi/./Waseda Univ.), Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta (Renesas Technology), Yasutaka Wada, Keiji Kimura, Hironori Kasahara (Waseda Univ.) SDM2007-143 ICD2007-71 |
This paper describes a heterogeneous multi-core processor (HMCP) architecture which integrates general purpose processor... [more] | SDM2007-143 ICD2007-71 pp.11-16 |
| RECONF | 2007-05-18 10:40 |
Ishikawa | Kanazawa Bunka Hall | A Study of the Dynamic Reconfigurable Processor Vulcan2 and Its Development Tool ISAcc Tetsuo Hiraki, Shingo Kadouchi, Yosuke Yamazaki (Kyushu Univ.), Takayuki Kando, Lovic Gauthier, Victor Goulart Mauro Ferreira (FLEETS), Antoine Trouve (ISIT), Koji Inoue, Kazuaki Murakami (Kyushu Univ.) RECONF2007-13 |
Application specific extensions of a processor provide higher performance. In this paper, the authors propose``Vulcan2''... [more] | RECONF2007-13 pp.73-78 |
| VLD, IPSJ-SLDM | 2007-05-10 14:55 |
Kyoto | Kyodai Kaikan | A Modeling of Dynamically Reconfigurable Processor using SystemC Kouji Ueda, Junji Kitamichi, Kenichi Kuroda (The Univ. of Aidu) |
Recently, dynamically reconfigurable processors (DRPs) based on FPGA technology are proposed. DRPs are implemented on... [more] |
VLD2007-4 pp.19-24 |
| RECONF | 2005-12-01 14:45 |
Fukuoka | Kitakyushu International Conference Center | Mapping of FFT onto Reconfigurable Processor FE-GA Makoto Satoh, Hiroshi Tanaka, Takanobu Tsunoda, Masashi Takada, Yohei Akita, Masaki Ito (Hitachi, Ltd.) |
Dynamically reconfigurable processors are getting popular in the fields such as wireless LAN, Audio, and Video processin... [more] | RECONF2005-68 pp.55-60 |
| RECONF | 2005-05-12 10:30 |
Kyoto | Kyoto University | Execution Cycle Minimization Algorithm for Dynamic Reconfigurable Processors with Hierarchical Memory Structure Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
The dynamic reconfigurable processor is a device that can change interconnections between processor elements and process... [more] | RECONF2005-3 pp.13-18 |
| CPSY, VLD, IPSJ-SLDM | 2005-01-25 09:30 |
Kanagawa | A Reconfigurable Processor based on ALU array architecture with limitation on the interconnection Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase (SANYO Electric), Shinji Kimura (Waseda Univ.) |
Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is introduced. We propose the A... [more] | VLD2004-97 CPSY2004-63 pp.1-6 |
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