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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, SDM | 2012-08-03 16:20 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | A 40nm Ultra Low Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro (Keio Univ.)  SDM2012-88 ICD2012-56 |
This paper presents an ultra low power and low voltage successive approximation register (SAR) analog to digital convert... [more] | SDM2012-88 ICD2012-56 pp.139-144 |
| RECONF | 2012-05-29 11:00 |
Okinawa | Tiruru (Naha Okinawa, Japan) | Development of a demonstration system for Ultra-low-power FPGA with Fine-Grained Field-Programmable Threshold Voltage Control Takashi Kawanami (KIT), Masakazu Hioki (AIST), Yohei Matsumoto (Kaiyo Univ.), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) RECONF2012-5 |
The Flex Power FPGA is a new FPGA architecture which enabled high speed operation and low power-consumption by fine-grai... [more] | RECONF2012-5 pp.25-30 |
| SDM, ICD | 2011-08-25 10:25 |
Toyama | Toyama kenminkaikan | Power-Performance Estimation of Datta-Das Spin Transistor Yoshiyuki Kondo, Shigeru Kawanaka, Kanna Adachi (Toshiba) SDM2011-74 ICD2011-42 |
We report the results of power-performance analysis of Datta-Das spin transistor(SFET) in this paper. We clarified it... [more] |
SDM2011-74 ICD2011-42 pp.17-22 |
| ICD, ITE-IST | 2011-07-22 14:20 |
Hiroshima | Hiroshima Institute of Technology | Concise method of minimum power consumption design of CMOS amplifier using EXCEL sheet. Masayuki Uno (Linear Cell Design) ICD2011-33 |
This paper describes design method for the maximum bandwidth and the optimum transistor size of a CMOS amplifier at each... [more] | ICD2011-33 pp.101-106 |
| RECONF | 2010-05-14 14:05 |
Nagasaki | A translational system using dynamic reconfigurable processor Kei Kinoshita, Daisuke Takano, Tomoyuki Okamura, Tetsuhiko Yao, Yoshiki Yamaguchi (Univ. of Tsukuba) RECONF2010-17 |
The demand to capture a wide-angle and high-definition video stream has been risen for systems of surveillance, in-vehic... [more] | RECONF2010-17 pp.93-98 |
|
| LQE, OPE | 2009-06-19 15:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Compact and Low Power Consumption Wavelength Tunable Laser Using Silicon-Wire Ring Resonator Nobuhide Fujioka, Tao Chu, Emiko Saito (NEC Corp./OITDA), Masatoshi Tokushima, Shigeru Nakamura (NEC Corp.), Masashige Ishizaka (NEC Corp./OITDA) OPE2009-26 LQE2009-29 |
(To be available after the conference date) [more] | OPE2009-26 LQE2009-29 pp.55-58 |
| RECONF | 2009-05-14 14:30 |
Fukui | A Power of FPGA Reduction Using FPGA Routing Structure Based on the Small-World Network Shoichi Nishida (Kumamoto Univ.), Yuzo Nishioka (Hitachi-Omron Terminal Solutions, Corp.), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2009-4 |
The performance of field-programmable gate arrays(FPGA) has improved dramatically owing to new process technology. But, ... [more] | RECONF2009-4 pp.19-24 |
|
| ICD | 2008-12-11 13:30 |
Tokyo | Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan | [Poster Presentation]
Design of Low-Power Medical Devices Kenichi Matsunaga, Vo Minh Tuan, Satoshi Furuya, Takashi Kurashina, Akira Matsuzawa (Titech) ICD2008-113 |
[more] | ICD2008-113 pp.55-57 |
| ICD, ITE-IST | 2008-10-23 14:10 |
Hokkaido | Hokkaido University | [Invited Talk]
Analog design isuues of high-resolution and low-power ADCs using a low voltage supply and sub-micron proceses Kunihiko Gotoh (FUJITSU LABORATORIES LTD.) ICD2008-76 |
The demand for high-speed (≧30 MS/s), high-resolution (≧10 bit) and low-power operation analog-to-digital converters (AD... [more] | ICD2008-76 pp.101-106 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2008-03-28 09:50 |
Kagoshima | An Asynchronous IEEE754-standard Single-precision Floating-point Divider for FPGA Masayuki Hiromoto, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) DC2007-105 CPSY2007-101 |
Synchronous design methodology is widely used for today's digital circuits. However, it is difficult to reuse a highly-... [more] | DC2007-105 CPSY2007-101 pp.127-132 |
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| ICD, ITE-IST | 2007-07-26 08:55 |
Hyogo | CMOS voltage reference based on threshold voltage of a MOSFET Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) ICD2007-38 |
We developed a voltage reference circuit using MOSFETs operated in the subthreshold region, except for the MOS resistor ... [more] | ICD2007-38 pp.5-10 |
|
| RECONF | 2007-05-18 09:30 |
Ishikawa | Kanazawa Bunka Hall | Power Reduction of Dynamical Reconfigurable Processor MuCCRA Keiichiro Hirai (Keio Univ.), Seidai Takeda (SIT.), Takashi Nishimura, Youhei Hasegawa, Satoshi Tsutsumi (Keio Univ.), Kimiyoshi Usami (SIT.), Hideharu Amano (Keio Univ.) RECONF2007-11 |
Although dynamically recon gurable processors have received an attention as a cost-e ective o -load engine for mobile d... [more] |
RECONF2007-11 pp.61-66 |
| ICD | 2007-04-13 10:30 |
Oita | A 0.14pJ/b Inductive-Coupling Transceiver Noriyuki Miura, Hiroki Ishikuro (Keio Univ.), Takayasu Sakurai (Univ. of Tokyo), Tadahiro Kuroda (Keio Univ.) ICD2007-12 |
A 0.14pJ/b inter-chip inductive-coupling data transceiver is developed. By using a pulse-shaping circuit, the transmitte... [more] | ICD2007-12 pp.65-69 |
|
| RCS, AP, WBS, SR, MW, MoNA (Joint) |
2006-03-03 13:00 |
Kanagawa | YRP | 0.4 V, 5.6 mW InP HEMT V-band Low-Noise Amplifier MMIC Kenjiro Nishikawa, Takatomo Enoki, Suehiro Sugitani, Ichihiko Toyoda (NTT) |
This paper demonstrates the low-power operation of an InP HEMT 60-GHz band low-noise amplifier (LNA) MMIC. The device us... [more] | MW2005-180 pp.13-18 |
| ICD, SDM | 2005-08-19 11:35 |
Hokkaido | HAKODATE KOKUSAI HOTEL | Gate work-function modulation in SiON/poly-Si gate stacks, and its impact on low power devices
-- Advantage of sub-monolayer Hf at SiON/poly-Si interface -- Jiro Yugami (Renesas), Yasuhiro Shimamoto (Hitachi), Masao Inoue, Masaharu Mizutani, Takashi Hayashi, Katsuya Shiga, Fumiko Fujita, Jyunichi Tuchimoto, Yoshikazu Ohno, Masahiro Yoneda (Renesas) |
Gate work-function (WF) is controlled by incorporating sub-monolayer Hf at SiON/poly-Si interface. This technique provid... [more] | SDM2005-149 ICD2005-88 pp.37-42 |
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