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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2023-03-02 09:30 |
Okinawa | (Primary: On-site, Secondary: Online) |
 VLD2022-85 HWS2022-56 |
(To be available after the conference date) [more] | VLD2022-85 HWS2022-56 pp.73-78 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control Yusuke Yoshida, Kimiyoshi Usami (SIT) VLD2017-33 DC2017-39 |
Embedded memory macros are major central building blocks of any microprocessor and greatly affect power dissipation. In ... [more] | VLD2017-33 DC2017-39 pp.37-42 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 10:15 |
Kanagawa | Hiyoshi Campus, Keio Univ. | MTJ-based Nonvolatile Flip-Flop Circuit Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami (SIT) VLD2016-97 CPSY2016-133 RECONF2016-78 |
With the spread of portable devices in recent year, products with high performance and low power consumption are require... [more] | VLD2016-97 CPSY2016-133 RECONF2016-78 pp.175-180 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-29 17:40 |
Kanagawa | Hiyoshi Campus, Keio University | Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits Toshihiro Takeshita, Shinichi Nishizawa, AKM Mahfuzul Islam, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ) VLD2014-129 CPSY2014-138 RECONF2014-62 |
Simultaneous supply and threshold voltage tuning has a strong impact on the energy reduction of LSI circuits. Therefore,... [more] | VLD2014-129 CPSY2014-138 RECONF2014-62 pp.111-116 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2014-10-02 13:25 |
Miyagi | Local pulse generation in variable stages pipeline designs for low energy consumption Takayuki Nii, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Univ.), Masao Yanagisawa (Waseda Univ.) VLD2014-61 ICD2014-54 IE2014-40 |
The increase of energy consumption due to improved performance has become a problem in the mobile terminal, and various ... [more] | VLD2014-61 ICD2014-54 IE2014-40 pp.7-12 |
|
| VLD | 2014-03-05 13:25 |
Okinawa | Okinawa Seinen Kaikan | Experiment and Analysis on Temperature Dependence of Delay and Energy for Subthreshold Circuits Hiroki Kushida, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.), Masao Yanagisawa (Waseda Univ.) VLD2013-161 |
Low voltage design has been used in order to reduce the energy dissipation of mobile network equipment. However, as supp... [more] | VLD2013-161 pp.147-151 |
| VLD | 2011-03-02 14:25 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Intra-task Analysis of Worst Case Execution Time and Average Energy Consumption on DEPS Framework Hirotaka Kawashima, Gang Zeng, Noritoshi Atsumi, Tomohiro Tatematsu, Hiroaki Takada (Nagoya Univ.) VLD2010-119 |
In this paper, we show an intra-task average energy consumption(AEC) and worst case execution time(WCET) analysis. The ... [more] | VLD2010-119 pp.19-24 |
| VLD | 2009-03-11 11:20 |
Okinawa | Execution Trace Mining for Intratask DVFS in Embedded Systems Tomohiro Tatematsu, Tetsuo Yokoyama, Takehiko Kikuchi, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.) VLD2008-128 |
We propose execution trace mining for intratask DVFS (dynamic voltage and frequency scaling) in embedded systems to effe... [more] | VLD2008-128 pp.11-16 |
|
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:05 |
Fukuoka | Kitakyushu International Conference Center | A Memory Management Technique for Energy Reduction in Multi-Task Embedded Applications Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
Memory systems consume a significant amount of the energy in embedded systems. Static code placement techniques using sc... [more] | VLD2007-74 DC2007-29 pp.25-29 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:30 |
Fukuoka | Kitakyushu International Conference Center | An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
This paper formulates a code placement problem to optimize the total energy consumption of a CPU core, on-chip memories ... [more] | VLD2007-75 DC2007-30 pp.31-36 |
| VLD, IPSJ-SLDM | 2006-05-11 15:00 |
Ehime | Ehime University | A Software-level Energy Reduction Technique for Embedded Microprocessor Exploiting Narrow Bitwidth Operations Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
This paper proposes a software-level energy reduction technique for microprocessor-based embedded systems. A basic idea ... [more] | VLD2006-3 pp.13-18 |
| RECONF | 2005-09-16 10:30 |
Hiroshima | A method of low energy design over an autonomous reconfiguration technique Shigeki Imai, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
High power consumption is a constraining factor for Reconfigurable Devices growth. We aim at reducing energy consumpt... [more] |
RECONF2005-44 pp.19-24 |
|
| ICD, SDM | 2005-08-18 08:55 |
Hokkaido | HAKODATE KOKUSAI HOTEL | An Energy Reduction Method for FFT Circuits in Digital Wireless Communications Using Bitwidth Control Masayuki Tokunaga, Kosuke Tarumi, Hiroto Yasuura (Kyushu Univ.) |
Recently, digital wireless communication systems become very popular to use in portable devices. Low-energy system imple... [more] | SDM2005-129 ICD2005-68 pp.7-12 |
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