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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2017-04-21 10:00 |
Tokyo | [Invited Lecture]
A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic Harsh N. Patel, Abhishek Roy, Farah B. Yahya, Ningxi Liu, Benton Calhoun (UVA), Akihiko Harada (FEA), Kazuyuki Kumeno, Makoto Yasuda, Taiji Ema (MIFS)  ICD2017-11 |
This paper presents an Ultra-Low Leakage (ULL) 55nm Deeply Depleted Channel (DDC) process technology. The 6T SRAM array ... [more] | ICD2017-11 pp.57-61 |
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| ICD | 2013-04-12 15:30 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Lecture]
Reduction of SRAM Standby Leakage utlizing All Digital Current Comparator Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki (Renesas Electronics) ICD2013-21 |
A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has two low-vo... [more] | ICD2013-21 pp.109-114 |
| ICD, SDM | 2008-07-17 15:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention Norifumi Kameshiro, Takao Watanabe, Tomoyuki Ishii, Toshiyuki Mine (Hitachi, Ltd.), Toshiaki Sano (Renesas), Hidefumi Ibe, Satoru Akiyama (Hitachi, Ltd.), Kazumasa Yanagisawa, Takashi Ipposhi, Toshiaki Iwamatsu, Yasuhiko Takahashi (Renesas) SDM2008-136 ICD2008-46 |
We proposed a fully logic compatible process for a single electron shut-off transistor (SESO). A 1-kb memory-cell array ... [more] | SDM2008-136 ICD2008-46 pp.47-52 |
| CPM, ED, LQE | 2007-10-12 09:50 |
Fukui | Fukui Univ. | Low leakage current ITO schottky electrode for AlGaN/GaN HEMT Keita Matsuda, Takeshi Kawasaki, Ken Nakata, Takeshi Igarashi, Seiji Yaegashi (Eudyna Devices) ED2007-167 CPM2007-93 LQE2007-68 |
AlGaN/GaN HEMTs are attractive devices for high power switching applications because of their high electron mobility and... [more] | ED2007-167 CPM2007-93 LQE2007-68 pp.57-61 |
| ICD, IPSJ-ARC | 2007-05-31 11:00 |
Kanagawa | A Study on Control Scheme of Awake Time in Drowsy Caches Ryotaro Kobayashi, Hideki Taniguchi, Toshio Shimada (Nagoya Univ.) |
Recently static power due to the leakage current has been a major problem as process technology advances. Drowsy Cache ... [more] | ICD2007-18 pp.7-12 |
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| ICD | 2006-04-14 13:00 |
Oita | Oita University | [Special Invited Talk]
Low-Power Low-Voltage SRAM Design for Battery Operation Masanao Yamaoka (Hitachi, Ltd.) |
In the processors for mobile devices, the power consumption of the embedded SRAMs has large impact on the total power c... [more] |
ICD2006-17 pp.91-96 |
| ICD | 2005-12-15 15:15 |
Kochi | Evaluation of energy consumption for High-Performance / Low-Leakage Caches based on Always Active line Reiko Komiya (Fukuoka Univ.), Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
So far we proposed a cache management technique to alleviate the negative effect of low-leakage caches. This technique m... [more] | ICD2005-189 pp.37-42 |
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| ICD | 2005-04-14 09:30 |
Fukuoka | Low-Power Embedded SRAM Modules with Expanded Margins for Writing Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda (Renesas), Yoshihiro Shinozaki (Hitachi ULSI), Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa (Renesas), Takayuki Kawahara (Hitachi, Ltd.) |
The power consumption of a low-power SoC has a battery life of mobile appliances. The general SoCs have large on-chip SR... [more] | ICD2005-2 pp.7-12 |
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