| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 16:20 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
On Reducing Area Overhead of BIST for Approximate Multiplier Considering Truncated Bits Daichi Akamatsu, Shougo Tokai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)  VLD2023-60 ICD2023-68 DC2023-67 RECONF2023-63 |
Recently, approximate computing has attracted attention as a method to reduce power and area for error-tolerant applicat... [more] | VLD2023-60 ICD2023-68 DC2023-67 RECONF2023-63 pp.156-161 |
| SCE | 2023-10-31 09:35 |
Miyagi | RIEC, Tohoku Univ. (Primary: On-site, Secondary: Online) |
Design and demonstration of multipliers using adiabatic quantum-flux-parametron Yu Hoshika, Shohei Takagi, Tomoyuki Tanaka (YNU), Christopher L. Ayala, Nobuyuki Yoshikawa (YNU-IAS) SCE2023-16 |
Adiabatic quantum-flux-parametron (AQFP) logic is an emerging superconducting circuit technology, which is superior in t... [more] | SCE2023-16 pp.21-25 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-28 15:00 |
Kumamoto | (Primary: On-site, Secondary: Online) |
On reduction of test patterns for a Multiplier Using Approximate Computing Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ) VLD2022-23 ICD2022-40 DC2022-39 RECONF2022-46 |
In recent years, approximate computing has been used in error-tolerant applications. Several approximation methods have ... [more] | VLD2022-23 ICD2022-40 DC2022-39 RECONF2022-46 pp.25-30 |
| SCE | 2022-08-09 09:35 |
Online | Online | Design of Energy-Efficient Adiabatic Quantum-Flux-Parametron Multiplier Families Shohei Takagi, Tomoyuki Tanaka (YNU), Christopher Ayala, Nobuyuki Yoshikawa (IAS,YNU) SCE2022-1 |
Adiabatic Quantum Flux Parametron (AQFP) circuits are characterized by a power dissipation of 5 to 6 orders less than CM... [more] | SCE2022-1 pp.1-5 |
| VLD, HWS [detail] | 2022-03-07 10:00 |
Online | Online | A Heuristic Scheduling Algorithm with Variable-Cycle Approximate Operations in High-Level Synthesis Koyu Ohata, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2021-78 HWS2021-55 |
This paper studies a scheduling algorithm for high-level synthesis that takes into account the difference in delay betwe... [more] | VLD2021-78 HWS2021-55 pp.13-18 |
| SDM, ICD, ITE-IST [detail] | 2021-08-18 13:45 |
Online | Online | Performance Evaluation of Serial-Parallel Montgomery Multipliers for RNS Hiroyuki Tsubouchi, Mitsunaga Kinjo, Katsuhiko Shimabukuro (Univ. of the Ryukyus) SDM2021-40 ICD2021-11 |
Modulo operations are required in RNS (Residue Number System) which enables to perform highly parallel computation. Also... [more] | SDM2021-40 ICD2021-11 pp.54-57 |
| HWS, VLD [detail] | 2021-03-03 10:25 |
Online | Online | Evaluation on Approximate Multiplier for CNN Calculation Yuechuan Zhang, Masahiro Fujita, Takashi Matsumoto (UTokyo) VLD2020-68 HWS2020-43 |
Improving the accuracy of a convolutional neural network (CNN) typically requires larger hardware with more energy consu... [more] | VLD2020-68 HWS2020-43 pp.7-12 |
| HWS, VLD [detail] | 2021-03-04 09:55 |
Online | Online | High-level synthesis of approximate circuits with two-level accuracies Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritumeikan Univ.) VLD2020-80 HWS2020-55 |
This paper studies high-level synthesis (HLS) of approximate computing circuits with multiple accuracy levels. This work... [more] | VLD2020-80 HWS2020-55 pp.67-72 |
| MW, EST, EMCJ, PEM, IEE-EMC [detail] | 2020-10-23 09:00 |
Online | Online | Electromagnetic and Circuit Combined Simulation for DBM Integrated Orthogonal Dual Modes Resonator Tatsuki Kayashima, Eisuke Nishiyama, Ichihiko Toyoda (Saga Univ.) EMCJ2020-36 MW2020-50 EST2020-38 |
In this study, a simulation approach is applied to a resonator utilizing the nonlinear characteristics of double-balance... [more] | EMCJ2020-36 MW2020-50 EST2020-38 pp.66-71 |
| CS, CAS | 2020-02-27 12:10 |
Kumamoto | A Serial Multiplier based on Sequential Subtraction from Maximum Products and Its Negative Number Calculation Method Masahiro Nagata (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Daichi Ikeda (Sanyo Denken), Isao Kayano (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato (Okayama Prefectural Univ.) CAS2019-105 CS2019-105 |
In recent years, digital hearing aids have become widespread, but their battery life is only about several days. To solv... [more] | CAS2019-105 CS2019-105 pp.43-48 |
|
| MSS, CAS, SIP, VLD | 2019-07-31 16:45 |
Iwate | Iwate Univ. | Speedup of the Asynchronous Serial Multiplier by Concealing the Idle Phase for Digital Hearing Aids Masahiro Nagata (Okayama Prefectural Univ.), Masafumi Kondo, Isao Kayono (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Kazutami Arimoto, Yoichiro Sato (Okayama Prefectural Univ.) CAS2019-22 VLD2019-28 SIP2019-38 MSS2019-22 |
Recently, digital hearing aids with DSP have spread through, but their battery life has remained for only a few days. Fo... [more] | CAS2019-22 VLD2019-28 SIP2019-38 MSS2019-22 pp.99-104 |
| ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] | 2019-07-23 14:25 |
Kochi | Kochi University of Technology | Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier Mitsufumi Yamazaki, Junichi Sakamoto, Yuta Okuaki, Tsutomu Matsumoto (YNU) ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32 |
Since bilinear pairing is useful in realizing advanced cryptography, side channel security evaluation of its high-speed ... [more] | ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32 pp.151-156 |
| HWS, VLD | 2019-02-28 13:05 |
Okinawa | Okinawa Ken Seinen Kaikan | High-Speed and Noise-Tolerant High-Radix Tree Domino Adder Targeted to 65 nm FD-SOI Technology Kazuki Niino, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-112 HWS2018-75 |
Domino logic was introduced at the forefront of the LSI market in the 2000s for high-speed circuits. In recent years, h... [more] | VLD2018-112 HWS2018-75 pp.115-120 |
| HWS, ISEC, SITE, ICSS, EMM, IPSJ-CSEC, IPSJ-SPT [detail] | 2018-07-26 15:25 |
Hokkaido | Sapporo Convention Center | A Study on Systematic Insertion of Hardware Trojan Based on Path Delay Akira Ito, Rei Ueno, Naofumi Homma, Takafumi Aoki (Tohoku Univ.) ISEC2018-44 SITE2018-36 HWS2018-41 ICSS2018-47 EMM2018-43 |
This paper presents a non-reversible and analytical method for inserting a path delay hardware Trojan (PDHT). The conven... [more] | ISEC2018-44 SITE2018-36 HWS2018-41 ICSS2018-47 EMM2018-43 pp.349-356 |
| HWS | 2018-04-13 13:55 |
Fukuoka | Energy Evaluation of FPGA Pairing Implementation with Pipeline Modular Multiplier Yusuke Nagahama, Daisuke Fujimoto, Junichi Sakamoto, Tsutomu Matsumoto (YNU) HWS2018-5 |
Energy consumption and latency are important features of dedicated hardware bilinear pairing calculators. However publi... [more] | HWS2018-5 pp.23-28 |
|
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 11:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Considerations of Inside Structures for Approximate Multipliers Masahiro Inoue, Kaori Tajima, Hiroyuki Baba, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.) VLD2017-29 DC2017-35 |
Approximate arithmetic circuits are logic circuits which do not generate accurate arithmetic results.Approximate arithme... [more] | VLD2017-29 DC2017-35 pp.13-18 |
| AP | 2016-08-22 13:25 |
Nagasaki | Nagasaki Univ. | Configuration Study of Circularly Polarized Antennas Integrated with a Double-Balanced Multiplier Takahiro Ino, Eisuke Nishiyama, Ichihiko Toyoda (Saga Univ.) AP2016-72 |
Circularly polarized antennas based on a new principle using a double balanced multiplier are proposed to achieve small ... [more] | AP2016-72 pp.25-30 |
| IT, ISEC, WBS | 2016-03-10 14:30 |
Tokyo | The University of Electro-Communications | A Multiplier Architecture for Finite Field of 254bit-Prime Square Order Based on Pipelined 32bit Montgomery Multipliers Yusuke Nagahama, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) IT2015-116 ISEC2015-75 WBS2015-99 |
Bilinear Pairing is a major tool to realize advanced cryptographic functionality such as searchable encryption, aggregat... [more] | IT2015-116 ISEC2015-75 WBS2015-99 pp.95-100 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-01 13:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit Masato Tamura, Makoto Ikeda (Univ. of Tokyo) VLD2015-39 DC2015-35 |
In this paper, we investigated the implementation method of elliptic curve digital signature algorithm using self-synchr... [more] | VLD2015-39 DC2015-35 pp.7-12 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-07 13:25 |
Kagoshima | Design and Evaluation of a Floating-point Multiplier with Online Error Detection by Partial Duplication Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.) CPSY2014-181 DC2014-107 |
A floating-point multiplier with reduced precision error detection is proposed. It uses a truncated multiplier for chec... [more] |
CPSY2014-181 DC2014-107 pp.125-130 |
|
[Return to Top Page]