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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SCE |
2019-10-10 10:25 |
Miyagi |
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Analysis of Malfunction of an Adiabatic Quantum Flux Parametron 16-bit Kogge Stone Adder Tomoyuki Tanaka, Christopher L. Ayala, Olivia Chen, Ro Saito, Nobuyuki Yoshikawa (YNU) SCE2019-27 |
An adiabatic quantum flux parametron (AQFP) circuit is one of the energy efficient superconducting circuits. To demonstr... [more] |
SCE2019-27 pp.27-30 |
VLD |
2017-03-03 11:20 |
Okinawa |
Okinawa Seinen Kaikan |
Optimization of Parallel Prefix Adder Using Simulated Annealing Takayuki Moto, Mineo Kaneko (JAIST) VLD2016-127 |
In this report, simulated annealing based optimization of parallel prefix adders (PPA) is proposed. In order to construc... [more] |
VLD2016-127 pp.139-144 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] |
2011-03-18 11:20 |
Okinawa |
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Design Method of Easily Testable Parallel Adders under Delay Constraints Shinichi Fujii (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2010-75 DC2010-74 |
Recently, with the development of VLSI design and manufacturing technology, the scale of integrated circuits on a VLSI c... [more] |
CPSY2010-75 DC2010-74 pp.57-62 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] |
2010-03-28 14:35 |
Tokyo |
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A consideration of synthesis methods for easily testable parallel prefix adders Shinichi Fujii, Naofumi Takagi (Nagoya Univ.) CPSY2009-93 DC2009-90 |
Previously, synthesis methods of parallel prefix adders have been proposed. These methods primarily use circuit area and... [more] |
CPSY2009-93 DC2009-90 pp.489-493 |
DC |
2009-06-19 10:20 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Design method of easily testable parallel prefix adders Hidetoshi Suzuki, Naofumi Takagi (Nagoya Univ) DC2009-10 |
We propose a design method of easily testable parallel prefix adders. In a parallel prefix adder, the prefix computation... [more] |
DC2009-10 pp.1-6 |
CAS, SIP, VLD |
2007-06-22 13:20 |
Hokkaido |
Hokkaido Tokai Univ. (Sapporo) |
Arithmetic Module Generation Using Optimized Parallel Prefix Adders Yuki Watanabe, Naofumi Homma, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Totech) CAS2007-27 VLD2007-43 SIP2007-57 |
This paper presents an arithmetic module generator using parallel prefix adders. In the proposed system, parallel prefix... [more] |
CAS2007-27 VLD2007-43 SIP2007-57 pp.49-54 |
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