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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| MW, WPT | 2024-04-18 11:10 |
Kanagawa | Kanagawa University (Primary: On-site, Secondary: Online) |
Derivation of General-Purpose ηmax kQ Theoretical Formula and Evaluation of Practical Characteristics of S-SP Type Wireless Power Transfer Circuit
-- Relationship with X-N, X-S, X-P type kQ theoretical formula and evaluation of application to robust design against large fluctuations in k and R -- Hideaki Abe  WPT2024-1 MW2024-1 |
The formula that gives the maximum achievable efficiency ηmax in X-S type and X-P type magnetic coupled wireless power t... [more] | WPT2024-1 MW2024-1 pp.1-6 |
| ICTSSL, CAS | 2024-01-25 15:50 |
Kanagawa | (Primary: On-site, Secondary: Online) |
Design of high-frequency diplexer robust to variations in chip elements and conductor patterns based on cutoff frequency Shotaro Nakata, Koji Wada (UEC) CAS2023-95 ICTSSL2023-48 |
In this study, the diplexer composed of LPF (Low Pass Filter) and HPF (High Pass Filter) using chip elements and conduct... [more] | CAS2023-95 ICTSSL2023-48 pp.60-65 |
| VLD | 2016-03-01 11:20 |
Okinawa | Okinawa Seinen Kaikan | Timing-error-tolerant AES Cipher Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-123 |
With the technologies advance, the importance of crypto circuits is increasing as well. AES cipher is well known as theo... [more] | VLD2015-123 pp.73-78 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 10:05 |
Oita | B-ConPlaza | An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-81 DC2014-35 |
As process technologies advance, process and delay variation causes a complex timing design and in-situ timing error cor... [more] | VLD2014-81 DC2014-35 pp.57-62 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:55 |
Kagoshima | Suspicious timing error prediction using check points Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-67 DC2013-33 |
Due to advance process technologies, timing design of LSIs has become more difficult and the importance of timing error ... [more] | VLD2013-67 DC2013-33 pp.39-44 |
|
| ED | 2012-04-18 16:50 |
Yamagata | Yamagata University | Optical analysis and design of the anti-reflection coating for organic solar cells Shigeru Kubota, Kensaku Kanomata, Katsuaki Momiyama, Takahiko Suzuki, Fumihiko Hirose (Yamagata Univ.) ED2012-9 |
We developed a practical design method for antireflection coatings for organic solar cells. In this analysis, after the ... [more] | ED2012-9 pp.35-40 |
| SDM [detail] | 2008-11-14 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
[Invited]Robust Design of Embedded SRAM on Deep-submicron Technology Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Hirofumi Shinohara (Renesas Technology Corp.) SDM2008-178 |
We develop high-density SRAM module in deep-submicron CMOS technology with the variation tolerant assist circuits agains... [more] | SDM2008-178 pp.55-60 |
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