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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, CPSY, VLD, IPSJ-SLDM 2008-01-16
14:10		 Kanagawa Hiyoshi Campus, Keio University An optimization method of DMA transfer for the SRC-6 reconfigurable machine
Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2007-109 CPSY2007-52 RECONF2007-55		 DMA transfer between a CPU and an FPGA often becomes a bottleneck of current reconfigurable machines. To mitigate this p... [more] VLD2007-109 CPSY2007-52 RECONF2007-55
pp.25-30
SIP, ICD, IE, IPSJ-SLDM 2005-10-20
15:30		 Miyagi Ichinobo, Sakunami-Spa A Memory Controller that Reduces Latency of Cached SDRAM
Seiji Miura, Satoru Akiyama (Hitachi,Ltd) 		The proposed controller has two main control schemes, address-alignment control and dummy-cache control scheme. These tw... [more] SIP2005-110 ICD2005-129 IE2005-74
pp.89-93
ICD 2004-12-16
10:30		 Hiroshima   A Dynamic SDRAM-Mode Control Scheme for Low-Power Systems
Seiji Miura, Kazushige Ayukawa (Hitachi,Ltd) 		A dynamic SDRAM-mode-control scheme for low-power systems was developed and tested. The scheme is based on two dynamic c... [more] ICD2004-184
pp.7-11
IE, SIP, ICD, IPSJ-SLDM 2004-10-22
11:15		 Yamagata   Low-Latency and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications
Yasuo Sugure (Hitachi), Seiji Takeuchi (Renesas), Yuichi Abe, Hiromichi Yamada (Hitachi), Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka (Renesas), Takanori Shimura (Hitachi) 		A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been... [more] SIP2004-93 ICD2004-125 IE2004-69
pp.25-30
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