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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CAS, CS | 2023-03-01 14:50 |
Fukuoka | Kitakyushu International Conference Center (Primary: On-site, Secondary: Online) |
Memory access optimization for former process of pencil drawing style image conversion in High-level Synthesis Honoka Tani, Akira Yamawaki (Kyutech)  CAS2022-105 CS2022-82 |
To effectively use high-level synthesis, which automatically converts software to hardware, it is necessary to create so... [more] | CAS2022-105 CS2022-82 pp.53-58 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2018-03-07 16:10 |
Shimane | Okinoshima Bunka-Kaikan Bldg. | Optimization of Memory Accesses of Large Scale Graph Analysis Using Multiport and Multibank Memory Keigo Teramoto, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ.) CPSY2017-136 DC2017-92 |
Recently, large scale graph analysis is getting important in the development of the Web and social networks. And in the ... [more] | CPSY2017-136 DC2017-92 pp.101-106 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2017-03-09 15:30 |
Okinawa | Kumejima Island | Approach to Direct Memory Access for Tamper Resistant System using Secure Processor Rihito Suzuki, Takuya Kajiwara, Mizuki Miyanaga, Hidetsugu Irie, Shuichi Sakai (UTokyo) CPSY2016-138 DC2016-84 |
In an environment using secure processor to support secure program execution, because of its integrity check mechanism, ... [more] | CPSY2016-138 DC2016-84 pp.39-44 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 14:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Hash-table and Balanced-tree based FIB Architecture for CCN Routers Reducing Memory Accesses Kenta Shimazaki (Waseda Univ.), Takashi Aoki, Takahiro Hatano, Takuya Otsuka, Akihiko Miyazaki (NTT), Toshitaka Tsuda, Yong-Jin Park, Nozomu Togawa (Waseda Univ.) VLD2015-75 DC2015-71 |
In conventional IP network, an IP router just forwards a packet to another router. Recently, Content Centric Networki... [more] |
VLD2015-75 DC2015-71 pp.243-248 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 10:25 |
Kagoshima | Forwarding Unit Generation for Loop Pipelining in High-Level Synthesis Shingo Kusakabe, Tomohito Toyama, Kenshu Seto (Tokyo City Univ.) VLD2013-95 DC2013-61 |
In the loop pipelining of high-level synthesis, the reduction of initiation intervals (IIs) is very important. Existing ... [more] | VLD2013-95 DC2013-61 pp.245-249 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 14:35 |
Kagoshima | A Study on the Design of Processor System for Stream Processing Yusuke Sekihara, Koji Yamazaki, Akihiko Miyazaki (NTT) VLD2013-101 DC2013-67 |
Processing performance required for packet data transfer system has been improving year by year due to the high-speed da... [more] | VLD2013-101 DC2013-67 pp.287-292 |
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| NS | 2013-10-17 15:20 |
Hokkaido | Hokkaido Univ. | A GPU Offloading method for improving performance of checksum computation in the TCP/IP stack Yuuki Tsubouchi, Go Hasegawa, Yoshiaki Taniguchi, Hirotaka Nakano, Morito Matsuoka (Osaka Univ.) NS2013-101 |
The size of ethernet frames is becoming larger and larger due to the utilization of Ethernet Jumbo Frame option, especi... [more] |
NS2013-101 pp.67-72 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 14:30 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Proposal of Speculative Memory Access Mechanism Based on Snoop Cache Yuji Sekiguchi, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2012-47 |
Ratio of execution path is mostly dominated by up to two execution paths in program loops. We have developed the specula... [more] | CPSY2012-47 pp.1-6 |
| VLD | 2011-03-03 13:45 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | A Circuit Synthesis for High Speed Memory Access in System LSI Kazuya Kishida, Takashi Kambe (Kinki Univ.) VLD2010-130 |
In system LSI, large-scale data is accessed from off-chip memory in many cases, and the architecture design of the memor... [more] | VLD2010-130 pp.81-86 |
| ICD | 2010-12-16 15:10 |
Tokyo | RCAST, Univ. of Tokyo | [Poster Presentation]
Design of Memory Access Controller for FU Array Accelerator Shunsuke Shitaoka, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (NAIST) ICD2010-114 |
Our previously proposed FU (functional unit) array accelerator can achieve both high energy-efficiency and binary-compat... [more] | ICD2010-114 pp.95-96 |
| CPSY, DC (Joint) |
2010-08-03 - 2010-08-05 |
Ishikawa | Kanazawa Cultural Hall | A Consideration of Speculative Memory Access in Two-Path Limited Speculation System Hiroyoshi Jutori, Akihiro Fukuda, Tsubasa Tsuda, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2010-18 |
We have proposed two-path limited speculation method and a multi-core processor architecture PALS which based on the met... [more] | CPSY2010-18 pp.61-66 |
| IA, ICSS | 2010-06-17 13:55 |
Kyoto | Academic Center for Computing and Media Studies, Kyoto University | Automatic OEP Finding Method for Malware Unpacking Yuhei Kawakoya, Makoto Iwamura, Mitsutaka Itoh (NTT) IA2010-3 ICSS2010-3 |
Malware analysts have to first extract hidden original code from a packed executable to analyze malware functionalities,... [more] | IA2010-3 ICSS2010-3 pp.13-18 |
| RECONF | 2009-05-14 13:00 |
Fukui | Performance Evaluation of Reconfigurable Processor Hy-DiSC based on MeP Hardware Extension Ken'ichi Umeda, Takuro Uchida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ) RECONF2009-1 |
We have developed the reconfigurable processor Hy-DiSC for stream processing. Hy-DiSC processor consists of MeP and DS-H... [more] | RECONF2009-1 pp.1-6 |
|
| RECONF | 2009-05-15 10:30 |
Fukui | A Memory Access Optimization Method for Reconfigurable Systems Based on a Multithread Programming Model Keisuke Dohi, Sayaka Shida, Yuichiro Shibata, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri (Nagasaki Univ.) RECONF2009-11 |
Reconfigurable systems are known to be able to achieve higher performance than traditional microprocessor architecture f... [more] | RECONF2009-11 pp.61-66 |
|
| SR | 2008-07-31 13:55 |
Tokyo | NICT (Koganei,-city Tokyo) | An efficient memory access system for array processor in wireless comunication system Tomoyoshi Kobori, Katsutoshi Seki, James Okello, Masao Ikekawa (NEC) SR2008-23 |
This paper describes the efficient memory access system for array processor in wireless communication system. Today, the... [more] | SR2008-23 pp.37-42 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2008-03-27 15:30 |
Kagoshima | A VLSI Architecture of Parallel Hough Transform with Localized Voting Space Access Masayuki Goto, Kazuhiro Nakamura, Yoshikazu Asada, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) DC2007-97 CPSY2007-93 |
Hough transform is a computer vision algorithm, which detects lines and circles in a binary image. We propose a VLSI ar... [more] |
DC2007-97 CPSY2007-93 pp.79-84 |
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| ICD, IPSJ-ARC | 2007-05-31 17:15 |
Kanagawa | A high-throughput, low-power FFT circuits for OFDM based wireless communication systems Shinsuke Ushiki, Kazunori Shimizu, Koichi Nakamura, Satoshi Goto, Takeshi Ikenaga (Waseda Univ.) ICD2007-26 |
OFDM attracts attention in digital wireless communication systems. In the FFT circuit which is main processing of digita... [more] | ICD2007-26 pp.55-60 |
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| PN | 2005-04-20 10:50 |
Tokyo | Univ. of Electric-Commications | Implementation and Evaluation of MPI Library with Globus Toolkit for Establishing Lambda Computing Environment Mai Imoto, Eiji Taniguchi, Ken-ichi Baba, Masayuki Murata (Osaka Univ.) |
In recent years, the Grid technology has being studied and developed by many researchers. In the conventional Grid envi... [more] |
PN2005-2 pp.7-12 |
| CPSY, VLD, IPSJ-SLDM | 2005-01-26 14:40 |
Kanagawa | ASIP Architecture for Real-Time Graphical Effect Acceleration Tatsuhiro Yoshimura, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
Graphical effect processing realizes a variety of visual representation. In this paper, we propose an ASIP architectur... [more] |
VLD2004-118 CPSY2004-84 pp.49-54 |
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