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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2023-08-04 15:35 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
Improving Data Transfer Efficiency in Many-Core Systems with a RISC-V ISA Extension Masaru Nishimura, Yuxi Tan, Yoshiki Yamaguchi (Tsukuba Univ.)  RECONF2023-16 |
The difficulty of balancing usability and efficient use of PEs and insufficient memory bandwidth are major issues for ma... [more] | RECONF2023-16 pp.13-18 |
| HWS, VLD | 2019-02-27 16:45 |
Okinawa | Okinawa Ken Seinen Kaikan | Design of an FPGA-based Manycore Architecture with Selective Local/Global Memory Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-105 HWS2018-68 |
FPGA-based manycore architectures attract an increasing attention in order to realize high-performance embedded systems.... [more] | VLD2018-105 HWS2018-68 pp.73-78 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:30 |
Hiroshima | Satellite Campus Hiroshima | A Case Study on Memory Architecture Exploration for FPGA-based Manycores Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-53 DC2018-39 |
In the design of high-performance embedded systems, FPGA-based manycores attract an increasing attention. In embedded sy... [more] | VLD2018-53 DC2018-39 pp.101-106 |
| RECONF | 2014-09-18 15:45 |
Hiroshima | Challenge for Ultrafast 10K-Node NoC emulation on FPGA Thiem Van Chu, Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) RECONF2014-21 |
With thousands of cores in the near future NoC architectures, the simulation time is a serious problem that makes archit... [more] | RECONF2014-21 pp.23-28 |
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| SIS, IPSJ-AVM | 2014-09-12 10:00 |
Yamagata | SHONAI INDUSTRIAL PROMOTION CENTER | Evaluation of high performance computing platforms for embedded system Jun Sato (NIT, Tsuruoka), Masafumi Ohta (CTC) SIS2014-62 |
The importance of multi-core in embedded systems is increasing. Also, embedded systems are able to take advantage of hig... [more] | SIS2014-62 pp.73-76 |
| CPSY | 2013-10-03 11:10 |
Chiba | Makuhari Messe | TMR execution on SmartCore system for dependable many-core processors Ryosuke Sasakawa, Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) CPSY2013-32 |
In order to improve the chip-level dependability, we have proposed SmartCore system, NoC-based DMR(Dual Modular Redundan... [more] | CPSY2013-32 pp.7-12 |
| RECONF | 2013-09-19 13:50 |
Ishikawa | Japan Advanced Institute of Science and Technology | A Packet Classifier using Parallel EVMDD(k) Machine Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao (Meiji Univ.), Munehiro Matsuura (Kyushu Inst. of Tech.) RECONF2013-34 |
A decision diagram machine~(DDM) is a special-purpose processor that uses special instructions to evaluate a decision... [more] |
RECONF2013-34 pp.85-90 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:50 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Network Performance of Multifunction On-chip Router Architectures Shinya Takamaeda-Yamazaki, Naoki Fujieda, Kenji Kise (Tokyo Inst. of Tech.) CPSY2012-52 |
In order to improve the chip-level dependability, we have proposed SmartCore system, NoC-based DMR (Dual Modular Redunda... [more] | CPSY2012-52 pp.27-32 |
| ICD, IPSJ-ARC | 2012-01-20 13:10 |
Tokyo | [Invited Talk]
Overview of High Performance Digital Processor Technology Hiroo Hayashi (Toshiba Corp.) ICD2011-141 |
Evolution of high-performance digital technology has been ongoing. The author surveys the technology trends of high-per... [more] | ICD2011-141 pp.73-76 |
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| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 16:05 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Validation of FPGA-based Many-core Simulator ScalableCore System Shinya Takamaeda, Ryosuke Sasakawa, Kenji Kise (Tokyo Tech) VLD2010-112 CPSY2010-67 RECONF2010-81 |
We have proposed and been developing the ScalableCore system, FPGA-based simulation system for tile many-core architectu... [more] | VLD2010-112 CPSY2010-67 RECONF2010-81 pp.187-192 |
| RECONF | 2010-09-17 13:40 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Implementation and Evaluation of ScalableCore System 2.0 Yoshito Sakaguchi, Shinya Takamaeda, Kenji Kise (Tokyo Tech) RECONF2010-38 |
ScalableCore is a concept of prototyping system development by using a lot of FPGAs for Many-core architecture researche... [more] | RECONF2010-38 pp.121-126 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] | 2010-03-28 13:00 |
Tokyo | Design of Look-Ahead Router for Low Latency Real-Time On-Chip Networks Takuma Kogo, Nobuyuki Yamasaki (Keio Univ.) CPSY2009-89 DC2009-86 |
Scheduling algorithms are very important to realize a real-time system by using large-scale chip multiprocessors (CMPs).... [more] | CPSY2009-89 DC2009-86 pp.465-470 |
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| ICD, IPSJ-ARC, IPSJ-EMB | 2010-01-28 14:00 |
Tokyo | T.B.D. | [Invited Talk]
Realization of High Performance Computing using Massive-parallel Multi-core GPU
-- Computational Application of 512 32/64-bit processor cores integrated in a single-chip GPU -- Toru Baji (NV-Japan) ICD2009-108 |
To meet the rapid evolution of rendering algorithm, PC/WS GPU has been implemented as a general-purpose multi-core GPU. ... [more] | ICD2009-108 pp.39-44 |
| MSS | 2010-01-21 15:25 |
Aichi | Toyota Central R&D Labs. | Energy-aware core allocation for many-core processor based on the market-oriented programming Takuto Miyagi, Tatsushi Yamasaki (Setsunan Univ.) CST2009-41 |
Recently, a many-core processor, which has a large number of independent cores, has been developed. For utilizing such p... [more] | CST2009-41 pp.25-30 |
| CPSY | 2009-11-20 15:55 |
Kyoto | Campus Plaza Kyoto | A Study of Task Allocation Problem for Many-core Processor with Consideration of Network Traffic Shintaro Sano, Masahiro Sano, Shimpei Sato (Tokyo Inst. of Tech.), Takefumi Miyoshi (Tokyo Inst. of Tech./JST), Kenji Kise (Tokyo Inst. of Tech.) CPSY2009-40 |
In many-core architecture that has dozens of cores in processor, it is important to improve performance by using paralle... [more] | CPSY2009-40 pp.31-36 |
| RECONF | 2009-09-18 10:25 |
Tochigi | Utsunomiya Univ. | A Study of Scalable Prototyping System with Small-sized FPGAs Shimpei Watanabe, Shinya Takamaeda, Ken Kyou (Tokyo Inst. of Tech), Takefumi Miyoshi (Tokyo Inst. of Tech/JST), Kenji Kise (Tokyo Inst. of Tech) RECONF2009-31 |
In order to practically simulate many-core processor, the authors proposed ScalableCore which is a hardware simulator. ... [more] |
RECONF2009-31 pp.73-78 |
| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | * Yuri Nishikawa (Keio Univ.), Michihiro Koibuchi (NII), Masato Yoshimi (Doshisha Univ.), Akihiro Shitara (Keio Univ.), Kenichi Miura (NII), Hideharu Amano (Keio Univ.) CPSY2009-25 |
ClearSpeed’s CSX600 that consists of 96 Processing Elements (PEs) employs a one-dimensional array topology for a simple ... [more] | CPSY2009-25 pp.91-96 |
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