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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-21
14:15		 Kanagawa Hiyoshi Campus, Keio University Write-Reduction using Encoding data on MLC for Non-Volatile Memories
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-107 CPSY2015-139 RECONF2015-89		 There is a movement to use the non-volatile memory to the important main memory in von Neumann computer.
Non-volatile m... [more]		 VLD2015-107 CPSY2015-139 RECONF2015-89
pp.221-225
ICD 2014-04-17
12:10		 Tokyo Kikai-Shinko-Kaikan Bldg. Design of Exchangeable MLC/TLC Hybrid Storage Array for Big Data
Shogo Hachiya, Koh Johguchi (Chuo Univ.), Kousuke Miyaji (Shinshu Univ.), Ken Takeuchi (Chuo Univ.) ICD2014-5		 A TLC-NAND flash provides a low cost and high capacity memory solution. However the reliability and access latency of TL... [more] ICD2014-5
pp.21-26
DC 2013-10-24
15:25		 Tokyo Kikai-Shinko-Kaikan Bldg. A Class of q-Ary Unidirectional Error Correcting Codes for MLC NAND Flash Memories
Shohei Kotaki, Masato Kitakami (Chiba Univ.) DC2013-25		 Error correcting codes (ECCs) are essential techniques to ensure reliability of NAND Flash Memories. As typical error so... [more] DC2013-25
pp.25-30
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