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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:30 |
Oita | B-ConPlaza | The LSI Implementation of a Memory Based Field Programmable Device for MCU Peripherals Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.), Hiroshi Makino (OIT), Kazutami Arimoto (Okayama Prefectural Univ.)  VLD2014-108 DC2014-62 |
A Field Programmable Sequencer and Memory (FPSM), which is an embedded memory based programmable device for peripherals ... [more] | VLD2014-108 DC2014-62 pp.239-244 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-07 10:30 |
Aomori | A Memory Based Filed Programmable Device for Energy saving MCUs Tetsuya Matsumura (Nihon Univ.), Yoshifumi Kawamura (Renesas Electronics), Naoya Okada (Kanazawa Univ.), Kazutami Arimoto (Okayama Prefectual Univ.), Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) VLD2013-46 ICD2013-70 IE2013-46 |
A Field Programmable Sequencer and memory (FPSM), which is an embedded memory based programmable peripherals for Micro C... [more] | VLD2013-46 ICD2013-70 IE2013-46 pp.1-6 |
|
| VLD | 2011-03-04 15:55 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Evaluation of Wiring Resource and Wiring Delay used in Via Programmable Logic Device VPEX Tatsuya Kitamori, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2010-147 |
We have developed a via programmable logic device using exclusive-or array (VPEX). In a VPEX, the logic is changed using... [more] | VLD2010-147 pp.183-188 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 10:20 |
Kochi | Kochi City Culture-Plaza | A Study of two input LUT array type programmable logic architecture for cryptographic processing Ai Nakanishi, Kouta Ishibashi, Yuuichirou Kurokawa, Takeshi Fujino (Ritsumeikan Univ.) RECONF2009-49 |
Various kinds of block ciphers must be supported in order to communicate safely in computer networks by using the consum... [more] | RECONF2009-49 pp.49-54 |
| SIS | 2009-03-05 15:45 |
Tokyo | [Special Talk]
System Realizations by Using Embedded Memories in FPGAs Yukihiro Iguchi (Meiji Univ.) |
FPGAs (Field Programmable Gate Arrays) have many embedded RAMs. We can use them for register files, FIFO (First In, Fi... [more] |
SIS2008-80 pp.49-54 |
|
| VLD, ICD | 2008-03-07 14:40 |
Okinawa | TiRuRu | Implementation and Evaluation of Network Security using An Embedded Programmable Logic Matrix (ePLX) Mitsutaka Matsumoto, Shun Kimura (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology Corp.), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.) VLD2007-165 ICD2007-188 |
Low Cost Network Appliance with low power microprocessor must be connected with networks in order to realize ubiquitous ... [more] | VLD2007-165 ICD2007-188 pp.53-58 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 10:15 |
Kanagawa | Hiyoshi Campus, Keio University | Improvement in data communication between PEs for SIMD type processor MX core Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) VLD2007-121 CPSY2007-64 RECONF2007-67 |
We are researching about MX Core developed in Renesas Technology Corp.. MX Core is SIMD(Single Instruction Multiple Data... [more] | VLD2007-121 CPSY2007-64 RECONF2007-67 pp.19-24 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:10 |
Fukuoka | Kitakyushu International Conference Center | A Development of the Auto mapping tool for embedded Programmable Logic matriX (ePLX) and the study of ePLX local architecture Kouta Ishibashi, Yoshiyuki Tanaka, Mitsutaka Matsumoto (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology), Masaya Yoshikawa (Meijo Univ.), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.) RECONF2007-32 |
We propose a ePLX(embedded Programmable Logic matriX)which will be embedded in SoC.The ePLX consists of small area and a... [more] | RECONF2007-32 pp.1-6 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 16:00 |
Fukuoka | Kitakyushu International Conference Center | Proposal and Circuit Performance Evaluation of Mask-less Via Programmable Device VPEX for EB Direct Writing Masahide Kawarasaki, Akihiro Nakamura, Tomoaki Nishimoto, Yoshiaki Shitabayashi, Takeshi Fujino (Ritsumeikan Univ.) VLD2007-80 DC2007-35 |
We propose the user-programmable device called VPEX (Via Programmable logic device using EXclusive-or array) which can c... [more] | VLD2007-80 DC2007-35 pp.61-66 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2007-01-18 13:25 |
Tokyo | Keio Univ. Hiyoshi Campus | Analysis of design architecture of ePLX ( embedded Programmable Logic matriX) and Evaluation of circuit mapping Tomoo Hishida, Kouta Ishibashi, Shun Kimura, Naoki Okuno, Mitsutaka Matsumoto (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.) |
Recently, non-recurring engineering costs (NREs), including cost of mask-sets, and engineering design efforts are critic... [more] | VLD2006-100 CPSY2006-71 RECONF2006-71 pp.37-42 |
| RECONF | 2006-05-18 15:15 |
Miyagi | TOHOKU UNIVERSITY | A performance evaluation of Matrix Processing Engine for media applications Takayuki Oono (Kumamoto Univ.), Hiroyuki Yamasaki (Renesas Tech.), Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
A performance gain in multimedia processing is demanded by the spread of mobile telephone or digital cameras. MTX (MaTri... [more] | RECONF2006-6 pp.31-36 |
| ICD | 2006-04-13 14:50 |
Oita | Oita University | [Special Invited Talk]
New Memory Device on SoC Platform Kazutami Arimoto (Renesas) |
Advanced SoC platform which is based on open architecture consists of hardware/ software interconnection and scalable c... [more] | ICD2006-7 pp.37-42 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2006-01-17 15:25 |
Kanagawa | Implementation of Stream Application on Programmable Devices by C Level Design Naohiro Katsura, Yohei Hasegawa, Vu Manh Tuan, Takamasa Kanamori, Hideharu Amano (Keio Univ.) |
While FPGA is a fine grain composition, the Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a... [more] | VLD2005-93 CPSY2005-49 RECONF2005-82 pp.31-36 |
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| RECONF | 2005-05-13 13:00 |
Kyoto | Kyoto University | [Invited Talk]
Programmable Device Technologies for SoC Embedded Applications Masami Nakajima, Hideyuki Noda, Kazutami Arimoto (Renesas) |
SoC for digital consumer market requires short time and low cost of development and easy system change. SoC development ... [more] | RECONF2005-21 pp.37-42 |
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