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Committee Date Time Place Paper Title / Authors Abstract Paper #
SCE 2009-10-20
13:00		 Tokyo Kikai-Shinko-Kaikan Bldg. A Logic Design Verification Method for SFQ Circuits Considering Pipeline Processing Behavior
Motoki Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ) SCE2009-17		 We propose a verification method of pipeline processing behavior of SFQ circuits. SFQ logic circuits work synchronously ... [more] SCE2009-17
pp.1-6
ICD, ITE-IST 2006-07-27
11:30		 Shizuoka   A study on the multi-bit-pipelined A/D converter
Hiroki Endou, Masaya Miyahara, Akira Matsuzawa (Titech) 		We have studied on the multi-bit pipeline A/D converter from the view pints of needed OP amp gain, needed capacitance, l... [more] ICD2006-63
pp.17-22
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