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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS | 2023-04-14 16:10 |
Oita | (Primary: On-site, Secondary: Online) |
An Application of Information Flow Tracking to Support Detection of Hardware Trojans Ryoichi Isawa, Nobuyuki Kanaya, Daisuke Inoue (NICT)  HWS2023-7 |
(To be available after the conference date) [more] | HWS2023-7 pp.26-31 |
| VLD, HWS [detail] | 2022-03-08 11:25 |
Online | Online | A Method for Automatic Test Pattern Generation using an SMT Solver for HDL Code Ryoichi Isawa, Nobuyuki Kanaya, Yoshitada Fujiwara, Tatsuta Takehisa, Hayato Ushimaru, Dai Arisue, Daisuke Makita, Satoshi Mimura, Daisuke Inoue (NICT) VLD2021-95 HWS2021-72 |
(To be available after the conference date) [more] | VLD2021-95 HWS2021-72 pp.105-110 |
| RECONF | 2018-09-18 14:50 |
Fukuoka | LINE Fukuoka Cafe Space | Data Flow Representation and its Applications to Machine Learning Accelerator Kazuki Nakada (Tsukuba Univ. of Tech.), Keiji Miura (Kwansei Gakuin Univ.) RECONF2018-32 |
Researches and development of machine learning accelerators have been rapidly progressing. It is becoming important to r... [more] | RECONF2018-32 pp.73-78 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 16:00 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Integrated Machine Code Monitor on FPGA Hiroaki Kaneko, Akinori Kanasugi (TokyoDenki Univ.) VLD2017-73 CPSY2017-117 RECONF2017-61 |
Machine code monitor is necessary for initial program development stage when implementing a new processor with unique IS... [more] | VLD2017-73 CPSY2017-117 RECONF2017-61 pp.65-70 |
| VLD | 2016-02-29 15:25 |
Okinawa | Okinawa Seinen Kaikan | A Multi-Paradigm High-Level Hardware Design Environment Shinya Takamaeda (NAIST) VLD2015-115 |
(To be available after the conference date) [more] | VLD2015-115 pp.25-30 |
| RECONF | 2015-09-18 13:25 |
Ehime | Ehime University | Design of Hardware Description Language FSL Based on Object-Oriented/Functional Programming Languages Nobuya Watanabe, Akira Nagoya (Okayama Univ.) RECONF2015-37 |
This paper presents a new hardware description language FSL. The FSL inherits the design philosophy and the language fea... [more] | RECONF2015-37 pp.27-32 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 10:45 |
Oita | B-ConPlaza | A hardware description method and sematics providing a timing constrant Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) VLD2014-82 DC2014-36 |
Formal verification methods are wide-spreading due to its mathmatical rigorousaspect, although they limited to synchroun... [more] | VLD2014-82 DC2014-36 pp.81-86 |
| CPSY | 2013-10-03 10:45 |
Chiba | Makuhari Messe | Design of a translator to Verilog HDL from hardware modeling language ArchHDL Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) CPSY2013-31 |
We have proposed ArchHDL as a new language for hardware RTL modeling. In ArchHDL, we realized continuous assignment and ... [more] | CPSY2013-31 pp.1-6 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 10:55 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Feasibility of JHDL for Dynamically Reconfigurable Hardware Design Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) VLD2010-103 CPSY2010-58 RECONF2010-72 |
To develop applications for dynamically reconfigurable hardware, the description language which increases the efficienc... [more] | VLD2010-103 CPSY2010-58 RECONF2010-72 pp.133-138 |
| RECONF | 2009-09-18 09:50 |
Tochigi | Utsunomiya Univ. | Comparison and Evaluation of Application Implementation Methods for Dynamically Reconfigurable Processor DAPDNA-2 Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ) RECONF2009-30 |
Design tools are essential to implement applications on dynamically reconfigurable hardware efficiently, therefore to un... [more] | RECONF2009-30 pp.67-72 |
| SCE | 2005-07-27 11:35 |
Aomori | Hirosaki Univ. | Automatic logic synthesis scheme and tool implementation for Single-Flux-Quantum circuits Yoshio Kameda, Shinichi Yorozu, Yoshihito Hashimoto (SRL) |
Single-flux-quantum (SFQ) logic circuits provide us a faster operation with low power consumption using Josephson juncti... [more] | SCE2005-17 pp.27-32 |
| CAS, SIP, VLD | 2005-06-28 13:50 |
Miyagi | Tohoku University | Formal Design of Arithmetic Circuits with Arithmetic Description Language: ARITH Yuki Watanabe, Naofumi Homma, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Tohtech) |
This paper presents a design of parallel multipliers based on arithmetic description language called ARITH. The multipli... [more] | CAS2005-21 VLD2005-32 SIP2005-45 pp.37-42 |
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