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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-15 10:45 |
Ehime | Ehime Prefecture Gender Equality Center | [Keynote Address]
Co-optimization of hardware architecture and algorithm for energy-efficient CNN inference Daisuke Miyashita (Kioxia)  VLD2019-47 ICD2019-36 IE2019-42 CPSY2019-46 DC2019-71 RECONF2019-42 |
(To be available after the conference date) [more] | VLD2019-47 ICD2019-36 IE2019-42 CPSY2019-46 DC2019-71 RECONF2019-42 p.173(VLD), p.41(ICD), p.41(IE), p.53(CPSY), p.173(DC), p.31(RECONF) |
| ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] | 2019-07-24 14:10 |
Kochi | Kochi University of Technology | Design of Highly Efficient AES Hardware Architectures Based on Multiplicative-Offset Rei Ueno (Tohoku Univ.), Sumio Morioka (IST), Noriyuki Miura, Kohei Matsuda, Makoto Nagata (Kobe Univ.), Shivam Bhasin (NTU), Yves Mathieu, Tarik Graba, Jean-Luc Danger (TPT), Naofumi Homma (Tohoku Univ.) ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61 |
This paper presents high throughput/gate hardware architectures. In order to achieve a high area-time efficiency, the pr... [more] | ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61 pp.375-382 |
| HWS, ICD | 2018-10-29 15:20 |
Osaka | Kobe Univ. Umeda Intelligent Laboratory | A Design and Implementation of Ring-LWE Cryptography Hardware Based on Number Theoretic Transform Sora Endo, Rei Ueno, Takafumi Aoki, Naofumi Homma (Tohoku Univ.) HWS2018-52 ICD2018-44 |
This paper presents an efficient Ring-LWE cryptographic hardware architecture based on number theoretic transformation. ... [more] | HWS2018-52 ICD2018-44 pp.31-34 |
| HWS | 2018-04-13 13:55 |
Fukuoka | Energy Evaluation of FPGA Pairing Implementation with Pipeline Modular Multiplier Yusuke Nagahama, Daisuke Fujimoto, Junichi Sakamoto, Tsutomu Matsumoto (YNU) HWS2018-5 |
Energy consumption and latency are important features of dedicated hardware bilinear pairing calculators. However publi... [more] | HWS2018-5 pp.23-28 |
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| IT, ISEC, WBS | 2016-03-10 14:30 |
Tokyo | The University of Electro-Communications | A Multiplier Architecture for Finite Field of 254bit-Prime Square Order Based on Pipelined 32bit Montgomery Multipliers Yusuke Nagahama, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) IT2015-116 ISEC2015-75 WBS2015-99 |
Bilinear Pairing is a major tool to realize advanced cryptographic functionality such as searchable encryption, aggregat... [more] | IT2015-116 ISEC2015-75 WBS2015-99 pp.95-100 |
| CAS | 2010-01-28 13:50 |
Kyoto | Kyoudai-Kaikan Bldg. | Tree Structured SOM Hardware by using hw/sw Complex Shuta Saito, Hakaru Tamukoh, Yuuichi Kobayashi, Masatoshi Sekine (Tokyo University of Agr and Tech.) CAS2009-66 |
Self-Organizing Map (SOM) is a neural network to get a statistical nature of multidimensional input data by self-organiz... [more] | CAS2009-66 pp.13-18 |
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