IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, CPSY 2015-12-17
10:40
Kyoto Kyoto Institute of Technology Improvement of TLB performance of MIPS-based processor
Gun Muto, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo (Mie Univ.) ICD2015-65 CPSY2015-78
TLB is onw of the important modules to enhance memory access performance. Generally, increasing the number of TLB entrie... [more] ICD2015-65 CPSY2015-78
pp.13-18
EMT, IEE-EMT 2015-06-12
13:25
Tokyo meeting room (1-5) of IEEJ Design Study of FDTD/FIT Dataflow Machine for Wider Applications
Hideki Kawaguchi (Muroran IT) EMT2015-5
For a purpose of practical use of microwave simulation technologies in industry applications, this paper presents a meth... [more] EMT2015-5
pp.25-30
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
11:25
Kanagawa   Low latency network topology using multiple links at each host
Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) VLD2012-128 CPSY2012-77 RECONF2012-82
End-to-end network latency has become an important issue for parallel application on large-scale High Performance Comput... [more] VLD2012-128 CPSY2012-77 RECONF2012-82
pp.123-128
DC, CPSY
(Joint)
2012-08-03
14:30
Tottori Torigin Bunka Kaikan Rack Layout Optimization for Random Network Topology
Ikki Fujiwara, Michihiro Koibuchi (NII) CPSY2012-25
As the scale of many-core parallel applications and supercomputer systems increases, the negative impact of communicatio... [more] CPSY2012-25
pp.97-102
OPE, EMT, MW 2008-07-24
14:50
Hokkaido   Interlocking Operation of FDTD/FIT Dedicated Computer PCB with Host PC
Yuya Fujita, Hideki Kawaguchi (Muroran IT) MW2008-66 OPE2008-49
Authors had been working in development of a dedicated computer for FDTD/FIT method to enhance ordinary personal compute... [more] MW2008-66 OPE2008-49
pp.109-112
EMT, OPE, MW 2007-08-02
09:00
Hokkaido Muroran Institute of Technology Higer Performace Architecture of FDTD/FIT Memory Machine
Yoshiyuki Fujishima, Yuya Fujita, Hideki Kawaguchi (Muroran IT), Shun-suke Matsuoka (Asahikawa NCT) MW2007-42 OPE2007-29
To achieve efficient design environment of electrical products based on microwave technologies, the authors have been wo... [more] MW2007-42 OPE2007-29
pp.1-6
 Results 1 - 6 of 6  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan