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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2011-12-16 17:10 |
Hyogo | Fault-tolerant Wormhole Switching with Partial Backtrack Capability Hiroki Kanai, Masato Kitakami (Chiba Univ.)  DC2011-75 |
Since a parallel computer and Network-on-Chip (NoC) have many elements, their failure rate is high. Fault-tolerance is i... [more] | DC2011-75 pp.39-44 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 13:25 |
Miyazaki | NewWelCity Miyazaki | An Integer Linear Programming based Multiple Task Allocation Method for Fault Tolerance in Network on Chip Hiroshi Saito (Univ. Aizu), Tomohiro Yoneda (NII), Yuichi Nakamura (NEC) VLD2011-77 DC2011-53 |
This paper proposes a multiple task allocation method for given NoC model, task graph, and the number of expected failur... [more] | VLD2011-77 DC2011-53 pp.147-152 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:55 |
Miyazaki | NewWelCity Miyazaki | Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application Takao Kawano (Tohoku Univ.), Naoya Onizawa (McGill Univ.), Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.) VLD2011-89 DC2011-65 |
In this paper, a new fine-grained power-gating technique is proposed. Fine-grained power-gating technique has the potent... [more] | VLD2011-89 DC2011-65 pp.215-220 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 09:25 |
Miyazaki | NewWelCity Miyazaki | A Priority-Aware On-Chip Network Router for Reducing Priority Inversions Yujiro Sasagawa, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) CPSY2011-50 |
With advances in fabrication technology, the number of cores on a chip multiprocessor (CMP) increases, and packet-switch... [more] | CPSY2011-50 pp.41-46 |
| DC, CPSY (Joint) |
2011-07-29 09:25 |
Kagoshima | 3-D Stacked Architecture using Inductinve Coupling Eiichi Sasaki, Daisuke Sasaki, Hiroki Matsutani, Hideharu Amano, Yasuhiro Take, Tadahiro Kuroda (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (TAT) CPSY2011-10 |
Cube-1: a low power heterogeneus 3-D stacked architecture using an inductive-coupling is proposed. A low power MIPS R3... [more] |
CPSY2011-10 pp.7-12 |
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| CAS | 2011-01-26 11:20 |
Kumamoto | Kumamoto University | On the Energy-Aware Mapping for NoCs Masayoshi Arai, Satoshi Tayu, Shuichi Ueno (Tokyo Inst. of Tech.) CAS2010-100 |
To overcome the complex communication problems that arise as the number of on-chip components increases, NoCs have been ... [more] | CAS2010-100 pp.87-92 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 10:10 |
Fukuoka | Kyushu University | A study of high-performance asynchronous network-on-chip focused on bias of packets transfer routes Satoshi Takeyasu, Masashi Imai, Hiroshi Nakamura (Tokyo Univ.) VLD2010-66 DC2010-33 |
GALS-NoC is recently paid attention. Beside, NoC have commonly bias of packets transfer routes by regularity of network ... [more] | VLD2010-66 DC2010-33 pp.67-72 |
| DC, CPSY | 2010-04-13 13:30 |
Tokyo | [Invited Talk]
Increasing Dependability based on Asynchronous Computation Tomohiro Yoneda (NII/Tokyo Tech.) CPSY2010-1 DC2010-1 |
As semiconductor process technology scales and device dimensions shrink, new types of faults, such as slow transistors d... [more] | CPSY2010-1 DC2010-1 p.1 |
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| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] | 2010-03-27 16:00 |
Tokyo | A Topology Decision Approach of IP Cores for Throughput Improvement of Application Specific NoC System Hiroshi Uchikoshi (TUT), Makoto Sugihara (TUT/JST) CPSY2009-88 DC2009-85 |
The continuous effort in shrinking the size of a transistor causes a wire delay to increase relatively faster than a gat... [more] | CPSY2009-88 DC2009-85 pp.321-326 |
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| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] | 2010-03-28 13:00 |
Tokyo | Design of Look-Ahead Router for Low Latency Real-Time On-Chip Networks Takuma Kogo, Nobuyuki Yamasaki (Keio Univ.) CPSY2009-89 DC2009-86 |
Scheduling algorithms are very important to realize a real-time system by using large-scale chip multiprocessors (CMPs).... [more] | CPSY2009-89 DC2009-86 pp.465-470 |
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| CPSY | 2009-11-20 15:55 |
Kyoto | Campus Plaza Kyoto | A Study of Task Allocation Problem for Many-core Processor with Consideration of Network Traffic Shintaro Sano, Masahiro Sano, Shimpei Sato (Tokyo Inst. of Tech.), Takefumi Miyoshi (Tokyo Inst. of Tech./JST), Kenji Kise (Tokyo Inst. of Tech.) CPSY2009-40 |
In many-core architecture that has dozens of cores in processor, it is important to improve performance by using paralle... [more] | CPSY2009-40 pp.31-36 |
| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | * Yu Kojima (Keio Univ.), Hiroki Matsutani (Univ. of Tokyo), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2009-24 |
We evaluate and propose a low-power method based on error-tolerant techniques in order to reduce the supply voltage whil... [more] | CPSY2009-24 pp.85-90 |
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| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | A robust on-chip asynchronous data-transfer scheme based on multi-level current-mode signalling Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.), Tomohiro Yoneda (NII) DC2009-18 |
This paper presents a robust on-chip asynchronous data-trasnfer circuit based on multi-level current-mode signalling und... [more] | DC2009-18 pp.1-6 |
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| VLD | 2009-03-12 13:25 |
Okinawa | A Proposal of an Adaptive Network on Chip for Multi-Core SoC Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ) VLD2008-146 |
The Network-on-Chip (NoC) for today’s multi/many-core architecture should be evaluated by its power dissipation rather t... [more] | VLD2008-146 pp.117-122 |
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| VLD | 2009-03-12 13:50 |
Okinawa | A hardmacro placement approach to reduce communication energy for deterministic-routing-based NoC Hiroshi Uchikoshi (Toyohashi Univ. of Tech.), Makoto Sugihara (Toyohashi Univ. of Tech./JST-CREST) VLD2008-147 |
An on-chip bus architecture is utilized as a communication architecture of a System-on-a-Chip. It is difficult to incre... [more] |
VLD2008-147 pp.123-128 |
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| VLD | 2009-03-12 14:15 |
Okinawa | Automatic generation of Network-on-Chip topology under link length and latency constraint Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida (Univ. of Tokyo/JST-CREST), Takeshi Matsumoto (Univ. of Tokyo), Masahiro Fujita (Univ. of Tokyo/JST-CREST) VLD2008-148 |
With wire delay becoming dominant compared to transistor delay in deep-submicron era, the performance of SoC is more aff... [more] | VLD2008-148 pp.129-134 |
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| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:10 |
Fukuoka | Kitakyushu International Conference Center | A Method for Optimizing Communication Architecture on Network-on-Chip Considering Chip Size and Wiring Costs Daisuke Hayashi, Wataru Murai (Osaka Univ.), Akio Nakata (Hiroshima City Univ.), Tomoya Kitani, Keiichi Yasumoto (NAIST), Teruo Higashino (Osaka Univ.) CPSY2007-35 |
In this paper, we propose a method for deriving an optimal Network-on-Chip (NoC) communication architecture using intege... [more] | CPSY2007-35 pp.1-6 |
| ICD, IPSJ-ARC | 2007-06-01 16:15 |
Kanagawa | Design of a highly parallel VLSI processor based on functional-unit-level packet data transfer scheme Yoshichika Fujioka, Nobuhiro Tomabechi (Hachinohe Inst. Tech.), Michitaka Kameyama (Tohoku Univ.) ICD2007-34 |
Until now, network on chip technology based on course grain packet data transfer was proposed. In this paper, fine grain... [more] | ICD2007-34 pp.103-108 |
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