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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-17
14:30		 Kanagawa Keio Univ (Hiyoshi Campus) Design and check a ROHM 0.18μm chip with Alliance VHDL toolset -- Trial the layout and netlist check tools --
Tatsuya Hosokawa, Hiroshi Imai, Naohiko Shimizu (Tokai Univ.) VLD2010-93 CPSY2010-48 RECONF2010-62		 In this paper, We describe about LSI design with an Alliance CAD tools. An alliance CAD tools is not
enough description... [more]		 VLD2010-93 CPSY2010-48 RECONF2010-62
pp.55-61
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