| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| AP | 2021-12-16 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
Stacked Patch Antenna Consisting of Exciting Element on Thin Layer and Parasitic Element on Substrate Takashi Maruyama, Hiroyuki Aoyama, Toru Takahashi, Masataka Otsuka (Mitsubishi Electric)  AP2021-132 |
In high frequency bands like millimeter wave, antennas might be formed on wiring layers of ICs. We assume to use patch a... [more] | AP2021-132 pp.19-24 |
| EST | 2019-05-17 14:40 |
Aichi | Nagoya Inst. Tech. | Dielectric Constant Change of Silicon Substrate after H/He Ion Irradiation for Loss Reduction Takuichi Hirano (Tokyo City Univ.), Maya Mizuno (NICT), Ning Li (Sophia Univ.), Takeshi Inoue, Masatsugu Sogabe (SHI-ATEX), Kenichi Okada (Tokyo Tech.) EST2019-5 |
The hydrogen (H) or helium (He) ion irradiation on a silicon (Si) substrate had been proposed to reduce loss in high fre... [more] | EST2019-5 pp.19-23 |
| EST, MW, EMCJ, IEE-EMC [detail] | 2018-10-19 11:35 |
Aomori | Hachinohe Chamber of Commerce and Industry(Hachinohe city, Aomori) | A Study of Loss Reduction in 60 GHz Band Silicon CMOS On-Chip Dipole Antenna using TSV Takuichi Hirano (Tokyo City Univ.) EMCJ2018-51 MW2018-87 EST2018-73 |
60 GHz CMOS on-chip antenna is low radiation efficiency due to large loss of silicon (Si) substrate. It is reported that... [more] | EMCJ2018-51 MW2018-87 EST2018-73 pp.105-109 |
| EMCJ, IEE-EMC, MW, EST [detail] | 2015-10-23 15:00 |
Miyagi | Sakura Hall, Katahira Campus, Tohoku Univ. | Design of Low Loss 60 GHz CMOS On-Chip Dipole Antenna By Helium-3 Ion Irradiation Takuichi Hirano, Ning Li, Kenichi Okada, Akira Matsuzawa, Jiro Hirokawa, Makoto Ando (Tokyo Tech.), Tsuyoshi Inoue, Hitoshi Sakane (SHIEI) EMCJ2015-79 MW2015-118 EST2015-89 |
60 GHz CMOS on-chip antenna is low radiation efficiency due to large loss of silicon (Si) substrate. In this paper, a 60... [more] | EMCJ2015-79 MW2015-118 EST2015-89 pp.123-127 |
| RCS, AP (Joint) |
2013-11-20 15:50 |
Shimane | Matsue Terrsa | Electromagnetic Simulation of Radiation Efficiency Improvement for an On-chip Antenna by a High Resistivity Substrate Supposing Ion Irradiation Yuki Yao, Takuichi Hirano, Kenichi Okada, Jiro Hirokawa, Makoto Ando (Titech) AP2013-104 |
We have analyzed on-chip antennas integrated in CMOS using a partially low loss Si substrate by the electromagnetic fiel... [more] | AP2013-104 pp.25-30 |
| EST, EMCJ, IEE-EMC [detail] | 2012-10-25 15:30 |
Miyagi | Tohoku Gakuin University(Tagajo Campus) | Electromagnetic Simulation of Radiation Efficiency for On-Chip Dipole/Loop/Patch Antennas on a Si CMOS Substrate Takuichi Hirano, Kenichi Okada, Jiro Hirokawa, Makoto Ando (TokyoTech) EMCJ2012-73 EST2012-57 |
Electromagnetic simulation of radiation efficiency for on-chip dipole, loop and patch antennas were performed. It was co... [more] | EMCJ2012-73 EST2012-57 pp.55-60 |
| MW | 2008-12-12 11:15 |
Toyama | Toyama-Univ. Gofuku-camp. | Chip Antenna Integrated with Tuning Circuit for 1seg D-TV Usage Kenichi Ishizuka, Hiroshi Nishida, Kazunari Kawahata (Murata Manufacturing Co.,Ltd.) MW2008-151 |
This paper proposes the miniaturized antenna for the cellular phone with 1-Seg system. Firstly we examined the matching ... [more] | MW2008-151 pp.31-36 |
| AP | 2007-06-21 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Small Size Dielectric Chip Antenna by Arranging Parasitic Element on the Back Side Osamu Shibata, Hiromasa Koyama, Takuma Sawaya (Murata Mfg.) AP2007-39 |
A new type antenna has been developed that characteristics are according to both of Yagi-Uda antenna with high F/B ratio... [more] | AP2007-39 pp.47-52 |
[Return to Top Page]