|
|
All Technical Committee Conferences (Searched in: All Years)
|
|
Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
|
Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD |
2016-03-01 11:20 |
Okinawa |
Okinawa Seinen Kaikan |
Timing-error-tolerant AES Cipher Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-123 |
With the technologies advance, the importance of crypto circuits is increasing as well. AES cipher is well known as theo... [more] |
VLD2015-123 pp.73-78 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 12:05 |
Nagasaki |
Nagasaki Kinro Fukushi Kaikan |
A Data-dependent Approximation-circuit Design using Timing-error Prediction Scheme and its Evaluations on FPGA Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-66 DC2015-62 |
The propagation delay and the transition probability along each path inside an LSI widely vary depending on input data, ... [more] |
VLD2015-66 DC2015-62 pp.183-188 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 09:40 |
Oita |
B-ConPlaza |
Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits Kazushi Kawamura, Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-80 DC2014-34 |
The propagation delay along each path inside an LSI widely varies depending on input data, and this property can be expl... [more] |
VLD2014-80 DC2014-34 pp.51-56 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 10:05 |
Oita |
B-ConPlaza |
An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-81 DC2014-35 |
As process technologies advance, process and delay variation causes a complex timing design and in-situ timing error cor... [more] |
VLD2014-81 DC2014-35 pp.57-62 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:55 |
Kagoshima |
|
Suspicious timing error prediction using check points Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-67 DC2013-33 |
Due to advance process technologies, timing design of LSIs has become more difficult and the importance of timing error ... [more] |
VLD2013-67 DC2013-33 pp.39-44 |
|
|
|
Copyright and reproduction :
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
|
[Return to Top Page]
[Return to IEICE Web Page]
|