| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2017-03-02 09:25 |
Okinawa | Okinawa Seinen Kaikan | FiCC: Crosstalk Noise Hardened Metal Fringe Capacitor for High Integration Naoyuki Miyagawa, Tomoya Kimura, Hiroyuki Ochi (Ritsumeikan Univ.)  VLD2016-109 |
In this paper, we propose Fishbone-in-Cage Capacitor (FiCC) that is a new variant of metal fringe capacitor (MFC), and s... [more] | VLD2016-109 pp.43-47 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 12:45 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | 2-step Charge Pump Voltage Booster Circuit for Micro Energy Harvesting Tomoya Kimura, Hiroyuki ochi (Ritsumeikan Univ.) VLD2016-46 DC2016-40 |
This report proposes L1L5-type 2-step charge pump circuit that is suitable for boosting efficiently the subthreshold inp... [more] | VLD2016-46 DC2016-40 pp.13-18 |
| ICD, SDM, ITE-IST [detail] | 2016-08-02 09:00 |
Osaka | Central Electric Club | [Invited Talk]
Soft Error Immunity of Ultra-Low Voltage SRAM Masanori Hashimoto (Osaka Univ.) SDM2016-54 ICD2016-22 |
This paper discusses soft error immunity of near-threshold/subthreshold SRAM. In terrestrial environment, high-energy ne... [more] | SDM2016-54 ICD2016-22 pp.53-58 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:15 |
Oita | B-ConPlaza | High speed design of sub-threshold circuit by using DTMOS Yuji Fukudome, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech), Masao Yanagisawa (Waseda Univ.) VLD2014-88 DC2014-42 |
Low power consumption is achieved by operating circuits in sub-threshold region. However, in sub-threshold region, the... [more] |
VLD2014-88 DC2014-42 pp.117-121 |
| VLD | 2014-03-05 13:25 |
Okinawa | Okinawa Seinen Kaikan | Experiment and Analysis on Temperature Dependence of Delay and Energy for Subthreshold Circuits Hiroki Kushida, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.), Masao Yanagisawa (Waseda Univ.) VLD2013-161 |
Low voltage design has been used in order to reduce the energy dissipation of mobile network equipment. However, as supp... [more] | VLD2013-161 pp.147-151 |
| ICD, ITE-IST | 2013-07-05 17:40 |
Hokkaido | San Refre Hakodate | Failure mode analysis for flip-flops at low voltages Takafumi Fujita, Junya Kawashima, Masayuki Hiromoto (Kyouto Univ.), Hiroshi Tsutsui (Hokkaido Univ.), Hiroyuki Ochi (Ritsumeikan Univ.), Takashi Sato (Kyouto Univ.) ICD2013-45 |
Towards the reducing power consumption, subthreshold circuit which operates at a low voltage below the threshold voltage... [more] | ICD2013-45 pp.129-134 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 09:00 |
Miyazaki | NewWelCity Miyazaki | [Invited Talk]
Ultra Low Voltage Subthreshold Circuit Design Masanori Hashimoto (Osaka Univ.) VLD2011-82 DC2011-58 |
Subthreshold circuits, which are drawing attention for ultra low-power applications, are reviewed in terms of power diss... [more] | VLD2011-82 DC2011-58 pp.173-178 |
| VLD | 2009-03-13 11:05 |
Okinawa | Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in Subthreshold Circuits Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ./JST-CREST) VLD2008-160 |
This paper presents modeling of manufacturing variability and body bias effect for subthreshold circuits based on mea... [more] |
VLD2008-160 pp.201-206 |
|
[Return to Top Page]