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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2014-03-05
16:10		 Okinawa Okinawa Seinen Kaikan Implementation of General-Synchronous Circuits into FPGA using Multi-Domain Clock Skew Scheduling
Tatsuya Masui, Yukihide Kohira (Univ. of Aizu) VLD2013-167		 Recently, instead of implementation into ASIC, implementation into FPGA is used in many fields. However, in general, cir... [more] VLD2013-167
pp.183-188
VLD 2009-03-11
16:15		 Okinawa   A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits
Shuhei Tani, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-135		 In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily si... [more] VLD2008-135
pp.53-58
SDM, VLD 2006-09-25
13:55		 Tokyo Kikai-Shinko-Kaikan Bldg. Peak Power Reduction in LSI by Clock Scheduling
Yosuke Takahashi, Atsushi Takahashi (Tokyo Tech) 		The reduction of peak power consumption of LSI is required to reduce the instability of gate operation, the delay increa... [more] VLD2006-35 SDM2006-156
pp.7-12
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