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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NS, NWS (Joint) |
2024-01-26 11:20 |
Hiroshima | Higashisenda Campus, HiroshimaUniversity + Online (Primary: On-site, Secondary: Online) |
Tiny Message Buffers for Real CNFs
-- Towards Extreme Cache Efficiency -- Ayuto Yamada, Ryota Kawashima (NITech), Hiroki Nakayama, Tsunemasa Hayashi (BOSCO), Hiroshi Matsuo (NITech)  NS2023-170 |
The basic packet forwarding efficiency of Cloud Native Network Functions (CNFs) exceeds 100 Mpps under ideal conditions. T... [more] | NS2023-170 pp.61-66 |
| HWS, VLD | 2023-03-02 16:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
Reducing Conflict Misses with Multiple Indexings in Compressed Caches Tasuku Fukami, Shinya Takamaeda (UTokyo) VLD2022-98 HWS2022-69 |
Cache memory is a common hardware mechanism that improves memory access performance. To enlarge cache capacity virtually... [more] | VLD2022-98 HWS2022-69 pp.131-136 |
| ICM | 2022-07-08 10:20 |
Hokkaido | Tokachi Plaza (Primary: On-site, Secondary: Online) |
[Encouragement Talk]
Comprehensive Evaluation to Determine Cache Action in vhost-user Daichi Takeya, Ryota Kawashima (NITech), Hiroki Nakayama, Tsunemasa Hayashi (BOSCO), Hiroshi Matsuo (NITech) ICM2022-18 |
Next generation network functions are expected to be deployed on highly advanced infrastrucures towards AI-based autonom... [more] | ICM2022-18 pp.42-47 |
| ICD | 2017-04-20 10:35 |
Tokyo | [Invited Lecture]
Sub-3 ns pulse with sub-100 uA switching of 1x-2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS Daisuke Saida, Saori Kashiwaad, Megumi Yakabe, Tadaomi Daibou, Junichi Ito, Hiroki Noguchi, Keiko Abe, Shinobu Fujita (Toshiba), Miyoshi Fukumoto, Shinji Miwa, Yoshishige Suzuki (Osaka Univ.) ICD2017-2 |
[more] | ICD2017-2 pp.5-9 |
|
| SDM | 2016-01-28 15:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2015-126 |
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for ... [more] | SDM2015-126 pp.27-30 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:50 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment Kaoru Saito, Ryotaro Kobayashi (Toyohashi Univ of Tech), Hajime Shimada (Nagoya Univ.) CPSY2015-72 |
Current CPU utilizes cache memory for decreasing an access speed gap between CPU and main memory. But the cache occupie... [more] |
CPSY2015-72 pp.63-68 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 14:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement Junya Goto, Nagisa Ishiura (K.G.) VLD2015-74 DC2015-70 |
This article proposes a method of reducing cache misses on an instruction memory by inserting offsets before basic block... [more] | VLD2015-74 DC2015-70 pp.237-241 |
| DC, CPSY | 2015-04-17 13:00 |
Tokyo | CGRA in Cache for Graph Applications Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-7 DC2015-7 |
Recently, CGRA has been suggested high-speed and lower power consumption of graph processing. Generally, CGRA is connect... [more] | CPSY2015-7 DC2015-7 pp.37-41 |
|
| SDM | 2015-01-27 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Low power and high memory density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques Kazutaka Ikegami, Hiroki Noguchi, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Takao Ochiai, Naoharu Shimomura, Shogo Itai, Daisuke Saida, Chika Tanaka, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2014-142 |
Due to difficulty to increase clock frequency, recent processors increase cache memory to improve performance. However, ... [more] | SDM2014-142 pp.29-32 |
| MRIS, ITE-MMS | 2014-10-03 09:30 |
Niigata | Kashiwazaki energy hall, Niigata | * Daisuke Saida, Naoharu Shimomura, Eiji Kitagawa, Chikayoshi Kamata, Megumi Yakabe, Yuuichi Osawa, Shinobu Fujita, Junichi Ito (Toshiba) MR2014-18 |
(To be available after the conference date) [more] | MR2014-18 pp.27-31 |
| CPSY | 2012-10-12 16:20 |
Hiroshima | Cache Memory Suitability for the Graph Analysis Workloads Noboru Tanabe (Toshiba), Sonoko Tomimori, Masami Takata, Kazuki Joe (Nara Women Univ.) CPSY2012-42 |
Graph500 is a benchmark suite for big data analysis which receives attention in these years. The spatial locality of spa... [more] | CPSY2012-42 pp.67-72 |
|
| KBSE, SS | 2012-07-28 14:20 |
Hokkaido | Future University Hakodate | Global Load Instruction Aggregation Considering Dimensions of Arrays Yasunobu Sumikawa, Munehiro Takimoto (TUS) SS2012-29 KBSE2012-31 |
Most of modern processors have some much faster cache memories than a main memory, and therefore, it is important to hit... [more] | SS2012-29 KBSE2012-31 pp.115-119 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 15:05 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Simultaneous Optimization of Cache Way Selection and Code Placement for Reducing the Memory Access Energy Consumption Junshi Takata (Kyushu Univ.), Tohru Ishihara (Kyoto Univ.), Koji Inoue (Kyushu Univ.) SIP2011-76 ICD2011-79 IE2011-75 |
The paper proposes a technique which simultaneously finds the optimal cache way allocation and code placement for given ... [more] | SIP2011-76 ICD2011-79 IE2011-75 pp.89-94 |
| VLD | 2011-03-02 14:00 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-118 |
In hierarchical cache configurations, L1 cache uses LRU as cache replacement policy but L2 and/or L3 caches use FIFO du... [more] |
VLD2010-118 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 09:30 |
Fukuoka | Kyushu University | Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-64 DC2010-31 |
The number of sets, block size and associativity determine processor's cache configuration. Particularly in embedded sys... [more] | VLD2010-64 DC2010-31 pp.55-60 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] | 2010-03-27 14:50 |
Tokyo | Quantitative Evaluation of Task-Switching Overhead in Cache Memory Mitsunori Serizawa, Makoto Sugihara (TUT) CPSY2009-85 DC2009-82 |
In the state-of-the-art computer systems trend, it is indispensable to have cache memory for high-speed processing, an... [more] |
CPSY2009-85 DC2009-82 pp.303-308 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 16:00 |
Kochi | Kochi City Culture-Plaza | Simulation-Based Bus Width Optimization for Two-Level Cache Shinta Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-48 DC2009-35 |
In this paper, we propose a simulation-based bus width and cache configuration optimization approach for two-level cache... [more] | VLD2009-48 DC2009-35 pp.43-48 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2009-03-05 15:15 |
Niigata | Sado Island Integrated Development Center | A Dynamic Management Technique of a Non-Uniform Selective Way Cache for Reducing the Energy Consumption of Embedded Processors Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) CPSY2008-90 DC2008-81 |
(To be available after the conference date) [more] | CPSY2008-90 DC2008-81 pp.13-18 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2009-03-05 15:45 |
Niigata | Sado Island Integrated Development Center | Single-Cycle-Accessible Two-Level Cache Architecture Seiichiro Yamaguchi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) CPSY2008-91 DC2008-82 |
A small L0-cache located between an MPU core and an L1-cache is widely used in embedded processors for reducing the ener... [more] | CPSY2008-91 DC2008-82 pp.19-24 |
| ICD, IPSJ-ARC | 2008-05-14 17:30 |
Tokyo | Quantitative Analysis of Memory Workload on Chip-Multiprocessors Mitsuaki Yamaguchi, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
Integrating multiple processor cores into a single chip, or chip-multiprocessors (CMPs) is one of the most promising ap... [more] |
ICD2008-37 pp.111-116 |
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