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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
11:15		 Kagoshima   Power Reduction of Non-volatile Logic Circuits Using the Minimum Writing Power Cut-set of State Registers
Yudai Itoi, Shinji Kimura (Waseda Univ.) VLD2013-82 DC2013-48		 Recently, the next generation non-volatile memory/register using magnetic tunnel junction elements has been paid attenti... [more] VLD2013-82 DC2013-48
pp.147-152
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